PC97338VLJ datasheet(84/221 Pages) NSC

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Section 3.1.2 on page 70 describes each mode and

“Bit 7 - System Operation Mode” on page 53 de-

scribes how each is enabled.

In PC-AT mode, bits 6 through 0 are in TRI-STATE to

prevent conflict with the status register of the hard

disk at the same address as the DIR.

FIGURE 52. DIR Register Bitmap

Bit 0 - High Density (PS/2 Mode Only)

In PC-AT mode, this bit is reserved, in TRI-STATE

and used by the status register of the hard disk.

In PS/2 mode, this bit indicates whether the data

transfer rate is high or low.

0 - The data transfer rate is high, i.e., 1 Mbps, 2

Mbps or 500 Kbps.

1 - The data transfer rate is low, i.e., 300 Kbps or

250 Kbps.

Bits 2,1 - Data Rata Select 1,0 (DRATE1,0)

(PS/2 Mode Only)

In PC-AT mode, these bits are reserved, in TRI-

STATE and used by the status register of the hard

disk.

In PS/2 mode, these bits indicate the status of the

DRATE1,0 bits programmed in DSR or CCR,

whichever is written last.

The significance of each value for these bits de-

pends on the supported speeds. See “Tape, SCCs

and Parallel Port Configuration Register (TUP),

Index 07h” on page 51. See also Table 40.

00 - Data transfer rate is 500 Kbps or invalid.

01 - Data transfer rate is 300 Kbps or invalid.

10 - Data transfer rate is 250 Kbps or invalid.

11 - Data transfer rate is 1 or 2 Mbps.

Bits 6-3 - Reserved

These bits are reserved and are always 1. In PC-

AT mode these bits are reserved and in TRI-

STATE. They are used by the status register of the

fixed hard disk.

Bit 7 - Disk Changed (DSKCHG)

This bit reflects the status of the DSKCHG disk in-

terface input signal.

During power down this bit is invalid, if it is read by

the software.

0 - DSKCHG is not active.

1 - DSKCHG is active.

3.3.10 Configuration Control Register

(CCR), Offset 111

This write-only register can be used to set the data

transfer rate.

The data transfer rate is programmed via the CCR,

not the DSR, for PC-AT, PS/2 and Micro Channel ap-

plications. Other applications can set the data transfer

rate in the DSR. See Section 3.3.7.

This register is not affected by a software reset.

The data rate of the floppy controller is determined by

the last write to either the CCR register or to the DSR

FIGURE 53. CCR Register Bitmap

Bits 1,0 - Data Transfer Rate Select 1,0

(DRATE 1,0)

These bits determine the data transfer rate for the

Floppy Disk Controller (FDC), depending on the

supported speeds. See “Tape, SCCs and Parallel

Port Configuration Register (TUP), Index 07h” on

page 51. Table 40 shows the data transfer rate se-

lected by each value of this field.

These bits are unaffected by a software reset, and

are set to 10 (250 Kbps) after a hardware reset.

Bits 7-2 - Reserved

These bits are reserved and should be set to 0.

543

Reset

Required

Digital Input

Offset 111

DRATE1 Status

DSKCHG

DRATE0 Status

Reserved

High Density

PS/2 Mode

Only

321

Reset

Required

Configuration Control

Offset 111

Reserved

DRATE1

DRATE0

PC97338VLJ Datasheet(PDF) 84 Page - National Semiconductor (TI)

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