PC97338VLJ datasheet(29/221 Pages) NSC

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IRRX1

IRRX2

Group 1

Infrared Received data signals 1 and 2. Infrared serial data input

signals. The infrared Analog Front End (AFE) is expected to send 1

to IRRX if there is no transmission. If it sends 0, the input signal

should be inverted by RXINV (bit 4 of register 7, in bank 7 of SCC2

- See Figure 88).

IRRX1 is multiplexed with SIN2.

IRRX2 is multiplexed with DSR2, IRQ12 and IRSL0.

IRSL0

IRSL1

IRSL2

43 or 49

41 or 47

Group 12

Infrared Control signals 0, 1 and 2. These signals control the

infrared Analog Front End (AFE).

IRSL0 is multiplexed with DSR2, IRQ12, IRRX2

(and ID0 in

PC97338).

IRSL1 is multiplexed with ID1 in PC97338.

IRSL2 is multiplexed with either DRV2, PNF, DR23, SIRQI3

(and

ID2 in PC97338), or with MTR1, IDLE (and ID2 in PC97338).

IRTX

Group 12

Infrared Transmitted data. Infrared serial data output.

IRTX is multiplexed with SOUT2, CFG0 (and BOUT2 in PC87338).

100

Group 1

Master Reset. Active high input signal that resets the controller to the

idle state. The configuration registers are set to their selected default

values. See the reset status for each functional unit.

MSEN0

MSEN1

(Normal

Mode)

Group 4

Media Sense signals 0 and 1. MSEN0 is selected as a media

sense input signal when bit 1 of the FCR register is 0. MSEN1 is

selected as a media sense input signal when bits 7 and 6 of the

SIRQ2 register are 00.

Each pin is internally connected to a 10 K

Ω pull-up resistor. When

bit 1 of FCR is 1, pin 52 is used as a Data Rate 0 output pin, and

the pull-up resistor is disabled.

When DACK3, DRATE1, CS0 or SIRQI2 is selected on the pin,

MSEN1 is masked to 1.

MSEN0 is multiplexed with DRATE0.

MSEN1 is multiplexed with DACK3, CS0, SIRQI2 and DRATE1.

MSEN0

MSEN1

(PPM

Mode)

Group 4

Media Sense signals 0 and 1. These signals provide additional

media sense signals in PPM mode when PNF = 0.

MSEN0 and MSEN1 are multiplexed with PD5 and PD7,

respectively. See Table 72 for more information.

MTR0

MTR1

(Normal

Mode)

Group 10

FDC Motor Select signals 0 and 1. These motor enable lines for

drives 0 and 1 are controlled by bits 7 through 4 of the Digital

Output register. They are active low output signals. They are

encoded with information to control four FDDs (MTR0 exchanges

logical motor values with MTR1) according to the TDR register

settings.

Bit 4 of the FCR register is reserved.

MTR1 is multiplexed with IDLE and IRSL2.

MTR1

(PPM

Mode)

Group 10

FDC Motor Select 1. This signal provides an additional motor select

1 signal in PPM mode when PNF = 0. It is active low. This pin is the

motor enable line for drive 1 or drive 0, according to the TDR

MTR1 is multiplexed with BUSY and WAIT. See Table 72 for more

information.

Symbol

PQFP

TQFP

I/O and

Group #

Function

PC97338VLJ Datasheet(PDF) 29 Page - National Semiconductor (TI)

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