 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PC97338VLJ Datasheet(PDF) 74 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
PC97338VLJ Datasheet(HTML) 74 Page - National Semiconductor (TI) |
|
|
74 / 221 page  74 www.national.com 3.3 THE REGISTERS OF THE FDC Legacy Mode In Legacy mode, the FDC registers are mapped to the offset address shown in Table 35, with the base ad- dress range provided by the on-chip address decod- er. For PC-AT or PS/2 applications, the primary address range of the diskette controller is 3F0 to 3F7h, and the secondary address range is 370 to 377h. TABLE 35. The FDC Registers and Their Addresses The FDC supports two system operation modes: PC-AT mode and PS/2 mode (micro-channel sys- tems). Section 3.1.2 on page 70 describes each mode and “Bit 7 - System Operation Mode” on page 53 de- scribes how each is enabled. Unless specifically indicated otherwise, all fields in all registers are valid in both modes. Plug and Play Mode In Plug and Play mode, the FDC has plug and play support, as follows: • The FDC interrupt can be routed on one of the fol- lowing ISA interrupts: IRQ3-IRQ7, IRQ9-IRQ12 and IRQ15 (see PNP2 register). • The FDC DMA signals can be routed to one of three 8-bit ISA DMA channels (see PNP2 regis- ter); and its base address is software configurable (see FBAL and FBAH registers). • Upon reset, the DMA of the FDC is routed to the DRQ2 and DACK2 pins. 3.3.1 FDC Register Bitmaps Symbol Description Offset R/W A2 A1 A0 SRA Status Register A 0 0 0 R SRB Status Register B 0 0 1 R DOR Digital Output Register 0 1 0 R/W TDR Tape Drive Register 0 1 1 R/W MSR Main Status Register 1 0 0 R DSR Data Rate Select Register 100 W FIFO Data Register (FIFO) 1 0 1 R/W - (Bus in TRI-STATE) 1 1 0 X DIR Digital Input Register 1 1 1 R CCR CCR Configuration Control Register 111 W 76 543 21 0 Reset Required 0 0 0 0 Status Register A (SRA) Offset 000 INDEX TRK0 Step DRV2 Head Direction WP Head Select IRQ6 Pending 76 54 321 0 Reset Required 1 1 1 0 0 0 1 1 1 1 Status Register B (SRB) Offset 001 WGATE WDATA DR0 Reserved Reserved MTR0 MTR1 RDATA 76 543 21 0 Reset Required 0 0 0 0 0 0 0 0 Digital Output Register (DOR) Offset 010 Reset Controller Motor Enable 0 Motor Enable 1 Motor Enable 2 Motor Enable 3 Drive Select DMAEN 76 54 321 0 Reset Required 0 0 1 Tape Drive Register (TDR) Offset 011 Reserved Valid Data High Density Extra Density Tape Drive Select1,0 Logical Drive Control 1,0 Automatic Media Sense and Enhanced TDR Drive Enhanced TDR Drive Mode Only Modes Only |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
