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L6758ATR Datasheet(PDF) 15 Page - STMicroelectronics

Part # L6758ATR
Description  DPM - dynamic phase management
PDF  42 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L6758ATR Datasheet(HTML) 15 Page - STMicroelectronics

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DocID023298 Rev 2
15/42
L6758A
VR12 serial data bus and IC configuration
42
4
VR12 serial data bus and IC configuration
The L6758A is fully compliant with Intel VR12/IMVP7 SVID protocol rev 1.5, document
# 456098. To guarantee proper device and CPU operation, refer to this document for bus
design and layout guidelines. Different platforms may require different pull-up impedance on
the SVI bus. Impedance matching and spacing among SVDATA, SVCLK and ALERT# must
be followed.
Table 6. VID table, both sections
HEX code
VOUT [V]
HEX code
VOUT [V]
HEX code
VOUT [V]
HEX code
VOUT [V]
0
0
0.000
4
0
0.565
8
0
0.885
C
0
1.205
0
1
0.250
4
1
0.570
8
1
0.890
C
1
1.210
0
2
0.255
4
2
0.575
8
2
0.895
C
2
1.215
0
3
0.260
4
3
0.580
8
3
0.900
C
3
1.220
0
4
0.265
4
4
0.585
8
4
0.905
C
4
1.225
0
5
0.270
4
5
0.590
8
5
0.910
C
5
1.230
0
6
0.275
4
6
0.595
8
6
0.915
C
6
1.235
0
7
0.280
4
7
0.600
8
7
0.920
C
7
1.240
0
8
0.285
4
8
0.605
8
8
0.925
C
8
1.245
0
9
0.290
4
9
0.610
8
9
0.930
C
9
1.250
0
A
0.295
4
A
0.615
8
A
0.935
C
A
1.255
0
B
0.300
4
B
0.620
8
B
0.940
C
B
1.260
0
C
0.305
4
C
0.625
8
C
0.945
C
C
1.265
0
D
0.310
4
D
0.630
8
D
0.950
C
D
1.270
0
E
0.315
4
E
0.635
8
E
0.955
C
E
1.275
0
F
0.320
4
F
0.640
8
F
0.960
C
F
1.280
1
0
0.325
5
0
0.645
9
0
0.965
D
0
1.285
1
1
0.330
5
1
0.650
9
1
0.970
D
1
1.290
1
2
0.335
5
2
0.655
9
2
0.975
D
2
1.295
1
3
0.340
5
3
0.660
9
3
0.980
D
3
1.300
1
4
0.345
5
4
0.665
9
4
0.985
D
4
1.305
1
5
0.350
5
5
0.670
9
5
0.990
D
5
1.310
1
6
0.355
5
6
0.675
9
6
0.995
D
6
1.315
1
7
0.360
5
7
0.680
9
7
1.000
D
7
1.320
1
8
0.365
5
8
0.685
9
8
1.005
D
8
1.325
1
9
0.370
5
9
0.690
9
9
1.010
D
9
1.330
1
A
0.375
5
A
0.695
9
A
1.015
D
A
1.335
1
B
0.380
5
B
0.700
9
B
1.020
D
B
1.340



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