L6758ATR datasheet(36/42 Pages) STMICROELECTRONICS

36 / 42 page

System control loop compensation

L6758A

36/42

DocID023298 Rev 2

Figure 12. Control loop bode diagram and fine tuning.

To obtain the desired shape, an R

-C

series network is considered for the Z

(s)

implementation. A zero at

=1/R

is then introduced together with an integrator. This

integrator minimizes the static error while placing the zero

in correspondence with the L-

C resonance, assuring a simple -20 dB/dec shape of the gain.

In fact, considering the usual value for the output filter, the LC resonance results at a

frequency lower than the above reported zero.

The compensation network can be designed as follows:

Equation 14

Equation 15

11.1

Compensation network guidelines

The compensation network design assures that the system responds according to the

crossover frequency selected and to the output filter considered: it is anyway possible to

further fine-tune the compensation network modifying the bandwidth in order to get the best

response of the system, as follows (see

Figure 12):

–

Increase R

to increase the system bandwidth accordingly

–

Decrease R

to decrease the system bandwidth accordingly

–

Increase C

to move

to low frequencies increasing, as a consequence, the

system phase margin.

Even though a fastest compensation network helps to satisfy the requirement of the load,

the inductor still limits the maximum dI/dt that the system can afford. In fact, when a load

transient is applied, the best that the controller can do is to “saturate” the duty cycle to its

maximum (d

MAX

) or minimum (0) value. The output voltage dV/dt is then limited by the

inductor charge/discharge time and by the output capacitance. In particular, the most

AM11145v1

ZF(s)

GLOOP(s)

LC = ωF

ESR

RF[dB]

ZF(s)

GLOOP(s)

LC = ωF

ESR

RF[dB]

ΔV

OS C

⋅

----------------------------------

------

⋅

ES R

()

----------------------------------

⋅⋅

⋅

--------------------

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