L6758ATR datasheet(25/42 Pages) STMICROELECTRONICS

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L6758A

Output voltage positioning

6.7

Dynamic VID transition support

The L6758A manages dynamic VID transitions that allow the output voltage of both sections

to be modified during normal device operation for power management purposes. OV, UV

signals are masked during every DVID transition and they are re-activated with proper delay

to prevent from false triggering.

When changing dynamically the regulated voltage (DVID), the system needs to charge or

discharge the output capacitor accordingly. This means that an extra-current I

DVID

needs to

be delivered (especially when increasing the output regulated voltage) and it must be

considered when setting the overcurrent threshold of both sections. This current results:

Equation 9

where dV

OUT

/ dT

VID

depends on the specific command issued (20 mV/

μsec. for

SetVID_Fast and 5 mV/

μsec. for SetVID_Slow).

Overcoming the OC threshold during the dynamic VID causes the device to latch and

disable.

As soon as the controller receives a new valid command to set the VID level for one (or

both) of the two sections, the reference of the involved section steps up or down according

to the target-VID with the programmed slope until the new code is reached. If a new valid

command is issued during the transition, the device updates the target-VID level and

performs the dynamic transition up to the new code. OV, UV are masked during the

transition and re-activated with proper delay after the end of the transition to prevent from

false triggering.

6.8

DVID optimization: REF/SREF

High slew rate for dynamic VID transitions cause overshoot and undershoot on the

regulated voltage causing a violation in the microprocessor requirement. To compensate

this behavior and to remove any over/undershoot in the transition, each section features

DVID optimization circuit.

The reference used for the regulation is available on the REF/SREF pin (see

Figure 7).

Connect an R

REF

to GND (R

SREF

/ C

SREF

for the single-phase) to optimize the DVID

behavior. Components may be designed as follows (multi-phase, same equations apply to

single-phase):

Equation 10

where

ΔVosc is the PWM ramp and k

the gain for the voltage loop (see

Section 11).

During a DVID transition, the REF pin moves according to the command issued

(SetVIDFast, SetVIDSlow); the current requested to charge/discharge the R

REF

DVID

OU T

VI D

------------------

⋅

RE F

ΔV

OS C

⋅

--------------------

–





⋅

RE F

⋅

RE F

-------------------

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