AMT49413 datasheet(8/21 Pages) ALLEGRO

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3-Phase BLDC Controller and MOSFET Driver

AMT49413

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

switching. The charge and discharge rate can be controlled using

external resistors in series with the connections to the gate of the

FETs.

RDEAD. Cross-conduction is prevented by the gate drive circuits

which introduce a dead time, tDEAD, between switching one FET

off and the complementary FET on. The dead time is derived

from the value of a resistor, RDEAD, connected between the

RDEAD pin and AGND. If RDEAD is connected to V5, tDEAD

defaults to 6 µs typical.

GLA, GLB, and GLC. Low-side gate drive outputs for external

NMOS drivers. External series-gate resistors, RGATE, (as close

as possible to the NMOS gate) can be used to control the slew

rate seen at the power-driver gate, thereby controlling the di/dt

and dv/dt of the Sx outputs. Referring to Table 2, GLx = 1 (high)

means that the upper half (PMOS) of the driver is turned on, and

that its drain will source current to the gate of the low-side FET

in the external motor-driving bridge. GLx = 0 (low) means that

the lower half (NMOS) of the driver is turned on, and that its

drain will sink current from the corresponding external FET gate

circuit to the LSS pin.

SA, SB, and SC. Directly connected to the motor, these termi-

nals sense the voltages switched across the load. These terminals

are also connected to the negative side of the bootstrap capacitors

and are the negative supply connections for the floating high-

side drivers. The discharge current from the high-side FET gate

capacitance flows through these connections, which should have

low-impedance traces to the FET bridge.

GHA, GHB, and GHC.High-sidegatedriveoutputsforexter-

nal NMOS drivers. External series-gate resistors, RGATE, can

be used to control the slew rate seen at the power-driver gate,

thereby controlling the di/dt and dv/dt of the Sx inputs. Referring

to Table 2, GHx = 1 (high) means that the upper half (PMOS) of

the driver is turned on, and that its drain will source current to the

gate of the high-side FET in the external motor-driving bridge.

GHx = 0 (low) means that the lower half (NMOS) of the driver

is turned on, and that its drain will sink current from the corre-

sponding external FET gate circuit to the respective Sx pin.

CA, CB, and CC.High-sideconnectionsforthebootstrap

capacitors and positive supply for high-side gate drivers. The

bootstrap capacitors, CBOOTx, are charged to approximately

VREG when the corresponding Sx terminal is low. When the Sx

output swings high, the voltage on the Cx pin rises with the out-

put to provide the boosted gate voltage needed for the high-side

N-channel power MOSFETs.

VDRAIN.High-impedancesenseinput(Kelvinconnection)to

the top of the external FET bridge. This input allows accurate

measurement of the voltage at the drain of the high-side FETs and

should be connected directly to the bridge, close to the drain con-

nections of the high-side FETs, with an independent trace.

LSS. Low-side return path for discharge of the gate capacitors.

It is connected to the common sources of the low-side external

FETs through an independent low-impedance trace.

Logic Control Inputs

Additional logic-level inputs are provided to enable specific

features described below. These logic inputs all have a nominal

hysteresis of 500 mV to improve noise performance.

RESET. Allows minimum current consumption from the VBB

supply. When RESET is low, all internal circuitry is disabled

including the V5 output. When coming out of sleep state, the

protection logic ensures that the gate drive outputs are off until

the charge pump reaches proper operating conditions. The charge

pump stabilizes in approximately 3 ms under nominal conditions.

RESEThasaninternalpull-downresistor,50kΩtypical.How-

ever, to allow the AMT49413 to start-up without the need for an

external logic input, the RESET pin can be pulled to the battery

voltage with an external pull-up resistor. Because RESET also has

an internal clamp diode, 6 V typical, to limit the input current, the

valueoftheexternalpull-upresistorshouldbegreaterthan20kΩ.

The upper limit for the resistor must be low enough to ensure that

the input voltage reaches the input high threshold, VINR.

COAST. An active-low input which turns all FETs off without

disabling the supplies or control logic. This allows the external

FETs and the motor to be protected in case of a short circuit.

MODE. Sets the current-decay method. Referring to Table 3,

when in slow-decay mode, MODE = 1, only the high-side MOS-

FET is switched off during a PWM-off cycle. In the fast-decay

mode, MODE = 0, the device switches both the high-side and

low-side MOSFETs.

Slow decay allows a lower ripple current in the motor at the

PWM frequency, but reduces the dynamic response of the cur-

rent control. It is suitable for motors which run at a more-or-less

constant speed. Fast decay provides improved current-control

dynamic response, but increases the motor current ripple. It is

suitable for motors used in start-stop and positioning applications.

DIR. Determines the direction of motor torque output, as shown

in Table 2. For an unloaded, low-inertia motor, this will also usu-

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