TS8388BCFS datasheet(49/57 Pages) ATMEL

49 / 57 page

TS8388B

2144C–BDC–04/03

(JITTER) Aperture

Uncertainty

Sample to sample variation in aperture delay. The voltage error due to jitter depends on the

slew rate of the signal at the sampling point.

(TS) Settling Time

Time delay to achieve 0.2% accuracy at the converter output when a 80% Full Scale step

function is applied to the differential analog input.

(ORT) Overvoltage

Recovery Time

Time to recover 0.2% accuracy at the output, after a 150% full scale step applied on the input

is reduced to midscale.

(TOD) Digital Data

Output Delay

Delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing point) to

the next point of change in the differential output data (zero crossing) with specified load.

(TD1) Time Delay from

Data to Data Ready

Time delay from Data transition to Data ready.

(TD2) Time Delay from

Data Ready to Data

General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock

period.

(TC) Encoding Clock

Period

TC1 = Minimum clock pulse width (high) TC = TC1 + TC2

TC2 = Minimum clock pulse width (low)

(TPD) Pipeline Delay

Number of clock cycles between the sampling edge of an input data and the associated output

data being made available, (not taking in account the TOD). For the TS8388B the TPD is 4

clock periods.

(TRDR) Data Ready

Reset Delay

Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB)

and the reset to digital zero transition of the Data Ready output signal (DR).

(TR) Rise Time

Time delay for the output DATA signals to rize from 20% to 80% of delta between low level

and high level.

(TF) Fall Time

Time delay for the output DATA signals to fall from 80% to 20% of delta between low level and

high level.

(PSRR) Power Supply

Rejection Ratio

Ratio of input offset variation to a change in power supply voltage.

(NRZ) Non Return to

Zero

When the input signal is larger than the upper bound of the ADC input range, the output code

is identical to the maximum code and the Out of Range bit is set to logic one. When the input

signal is smaller than the lower bound of the ADC input range, the output code is identical to

the minimum code, and the Out of range bit is set to logic one. (It is assumed that the input sig-

nal amplitude remains within the absolute maximum ratings).

(IMD) InterModulation

Distortion

The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to the

worst third order intermodulation products. The input tones levels are at -7 dB Full Scale.

(NPR) Noise Power

Ratio

The NPR is measured to characterize the ADC performance in response to broad bandwidth

signals. When using a notch-filtered broadband white-noise generator as the input to the ADC

under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the

average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output

sample test.

TS8388BCFS Datasheet(PDF) 49 Page - ATMEL Corporation

TS8388BCFS Datasheet(HTML) 49 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Datasheet Download

Link URL