TLE 6209 R

Data Sheet, Version 3.0

24

2001-10-15

Figure 6

Output Delay and Switching Time Definitions

Figure 7

Standard Data Transfer Timing

90%

10%

t

d1

t

RIS E

t

FALL

50%

50%

t

d2

V

OUT

PW M

Input

0

5

V

10%

90%

100%

D IR = L / H => V

R esistive load to V s =>

t

t

Resistive load to G N D =>

t

t

3

0

7

3

24

1

SDI

SCLK

CSN

0

7

6

5

4

3

2

1

SDO

CSN High to Low & rising edge of SCLK: SDO is enabled. Status informa ion is transfered to Output Shift Register

CSN Low to High: Data from Shift-Register is transfered to Output Driver Logic

previous Status

actual Data

SDI: Data will be accepted on the falling edge of CLK-Signal

SDO: State will change on the rising edge of CLK-Signal

__

_

_

_

_

_

_

time

0

0

0

+

new Data

actual Status

actual Data

old Data

1

2

0

7

6

5

4

56