PC87334VLJ datasheet(28/102 Pages) NSC

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20 Configuration Registers (Continued)

261 Recommended Power-Down MethodsGroup 1

Use the power-down methods in Group 1 to place the

PC87334 in one of the following modes

Mode 1

The entire chip is powered-down the crystal osci-

IIator is stopped pins are TRI-STATE and the in-

puts are blocked

In this mode the maximum current saving can be

achieved

Mode 2

The entire chip is powered-down the crystal os-

cillator is stopped Pins are driven

Mode 3

The entire chip is powered-down pins are TRI-

STATE and the inputs are blocked The crystal

oscillator operates and provides fast wake-up

Mode 4

The entire chip is powered-down Pins are driven

The crystal oscillator operates

There are 13 methods to reach the above four operating

modes See Table 2-11 Group 1

262 Recommended Power-Down MethodsGroup 2

Use the power-down modes in Group 2 to place the

PC87334 in any desired combination of the following power-

down modes

Mode 1

Parallel Port (SPPEPPECP) is powered-down

providing a savings of up to 5 mA

Mode 2

UARTs are powered-down providing a savings of

up to 5 mA

Mode 3

FDC is powered-down providing a savings of up

to 4 mA

Mode 4

IDE is powered-down providing a savings of up

to 01 mA

See also the PMC register

27 POWER-UP PROCEDURE AND CONSIDERATIONS

271 Crystal Stabilization

If the crystal is stopped by putting either the FDC or both

UARTs into low power mode then a finite amount of time

(E8 ms) must be allowed for crystal stabilization during

subsequent power-up

The stabilization period can be

sensed by reading the Main Status Register in the FDC if

the FDC is being powered up (The Request for Master bit is

not set for E8 ms) If either one of the UARTs are being

powered up but the FDC is not then the software must

determine the E8 ms crystal stabilization period Stabiliza-

tion of the crystal can also be sensed by putting the UART

into local loopback mode and sending bytes until they are

received correctly

272 UART Power-Up

The clock signal to the UARTs is controlled through the

Configuration Registers (FER PTR) In order to restore the

clock signal to one or both UARTs the following conditions

must exist

1 The appropriate enable bit (FER12) for the UART(s)

must be set

2 The Power-Down bit (PTR0) must not be set

3 If the PWDN pin option (PTR2 and FCR6) is used the

CSOUT PWDN ZWS pin must be inactive

If the crystal has been stopped follow the guidelines in

Section 271 before sending data or signaling that the re-

ceiver channel is ready

TABLE 2-11 Methods to Achieve Group 1 Power-Down Modes

Method

PTR Bits 012

Pin 3 (PQFP) or

FER Bits 01236

PCR Bit 2

PMC Bits 0126

Mode

Typical Current

Pin 1 (TQFP)

Consumption

(Note 3)

(Note 4)

11x

xxxxx

1111

110 mA

x10

xxxxx

1111

x1x

00000

1111

11x

xxxxx

0000

15 mA

x10

xxxxx

0000

x1x

00000

0000

x1x

xxx1x

0000

(Notes 1 2)

10x

xxxxx

1111

34 mA

x00

xxxxx

1111

x0x

00000

1111

10x

xxxxx

0000

55 mA

x00

xxxxx

0000

x0x

00000

0000

(Note 1)

Note 1

The PC87334 can also be placed in Mode 2 or Mode 4 using the strap configuration pins CFG0–4 (see Table 2-1)

Note 2

The PC87334 can also be placed in Mode 2 by using method

7 and entering FDC Low Power by executing Mode Command or by setting bit 6 of DSR to

high

Note 3

3 is PDWN input (configured when bit 2 of PTR is 0 and bit 6 of FCR is 1)

Note 4

These values are measured under the following conditions

1 No load on outputs

2 Inputs are stable

3 VIL e VSS VIH e VDD

4 VDD e 33V

5 FCR0 is 1 for UARTs 1 and 2 (16550 modeFIFO enabled)

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