PC87334VLJ datasheet(52/102 Pages) NSC

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40 FDC Command Set Description (Continued)

4122 Version Command

The Version command can be used to determine the floppy

controller being used The Result Phase uniquely identifies

the floppy controller version The FDC returns a value of

90h in order to be compatible with the 82077 The DP8473

and other NEC765 compatible controllers will return a value

of 80h (invalid command)

Command Phase

00010000

Execution Phase

None

Result Phase

10010000

4123 Write Data Command

The Write Data command receives data from the host and

writes logical sectors containing a Normal Data AM to the

selected drive The operation of this command is similar to

the Read Data command except that the data is transferred

from the mP to the controller instead of the other way

around

The controller will simulate the Motor On time before start-

ing the operation If implied seeks are enabled the seek and

sense interrupt functions are then performed The controller

then starts the Data Separator and waits for the Data Sepa-

rator to find the next sector Address Field The controller

compares the Address ID (track head sector bytes per

sector) with the desired ID specified in the Command

Phase If there is no match the controller waits to find the

next sector Address Field This process continues until the

desired sector is found If an error condition occurs the IC

bits in ST0 are set to Abnormal Termination and the con-

troller enters the Result Phase Possible errors are

1 The mP aborted the command by writing to the FIFO If

there is no disk in the drive the controller will hang up

The mP must then take the controller out of this hung

state by writing a byte to the FIFO This will put the con-

troller into the Result Phase

2 Two index pulses were detected since the search began

and no valid ID has been found If the track address ID

differs the WT bit or BT bit (if the track address is FFh)

will be set in ST2 If the head sector or bytes per sector

code did not match the ND bit is set in ST1 If the Ad-

dress Field AM was never found the MA bit is set in ST1

3 The Address Field was found with a CRC error The CE

bit is set in ST1

4 If the controller detects the Write Protect disk interface

input is Asserted Bit 1 of ST1 is set

If the correct Address Field is found the controller waits for

all (conventional mode) or part (perpendicular mode) of

GAP2 to pass The controller will then write the preamble

field address marks and data bytes to the Data Field The

data bytes are transferred to the controller by the mP

Having finished writing the sector the controller will contin-

ue reading the next logical sector unless one or more of the

following termination conditions has occurred

1 The DMA controller asserted TC The IC bits in ST0 are

set to Normal Termination

2 The last sector address (of side 1 if MT was set) was

equal to EOT The EOT bit in ST1 is set The IC bits in

ST0 are set to Abnormal Termination This is the expect-

ed condition during Non-DMA transfers

3 Underrun error The OR bit in ST1 is set The IC bits in

ST0 are set to Abnormal Termination If the mP cannot

service a transfer request in time the last correctly writ-

ten byte will be written to the disk

If MT was set in the Opcode command byte and the last

sector of side 0 has been transferred the controller will then

continue with side 1

PC87334VLJ Datasheet(PDF) 52 Page - National Semiconductor (TI)

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