PCM1860 datasheet(36/141 Pages) TI1

36 / 141 page

PCM1860-Q1, PCM1861-Q1, PCM1862-Q1

PCM1863-Q1, PCM1864-Q1, PCM1865-Q1

SLASE64A – DECEMBER 2014 – REVISED JUNE 2017

www.ti.com

Product Folder Links: PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1

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9.3.9.4.1

Clock Configuration and Selection for Hardware-Controlled Devices

The PCM1860-Q1 and PCM1861-Q1 hardware-controlled devices offer both master and slave functionality. In

master mode, a source master clock (of 256x, 384x, or 512x the sampling rate) can be sourced from either an

external crystal (XI/XO) or on an incoming SCK. (see the External Clock-Source Limits section for input rate

limitations on SCK sources) The clock from XI and SCK are OR-ed internally, allowing either to be used.

These hardware-controlled devices can generate the other I2S clocks (BCK and LRCK) in master mode (with

dividers set in MD0 and MD1) or be a clock slave to MCK,BCK and LRCK. In this scenario, the device auto-

detects the clock divider ratio.

In master mode, BCK per LRCK is fixed at 64, and allows up to 32 bits per channel.

Selection of the appropriate master or slave, and clock ratio between MCK and fS can be done using MD0 and

MD1.

Table 6 shows the suggested master clock rates for each of the sample rates supported. For slave mode, set

BCK per LRCK to 64.

Table 6. External Master Clock Rate Versus Sampling Frequency

SAMPLING RATE FREQUENCY

(kHz)

SYSTEM CLOCK FREQUENCY (MHz)

256 × fS

384 × fS

512 × fS

8.0

2.048

3.072

4.096

16.0

4.096

6.144

8.192

32.0

8.1920

12.2880

16.3840

44.1

11.2896

16.9344

22.5792

48.0

12.2880

18.4320

24.5760

64.0

16.3840

24.5760

32.7680

88.2

22.5792

33.8688

45.1584

96.0

24.5760

36.8640

49.1520

176.4

45.1584

—

192.0

49.1520

—

9.3.9.4.2

Clock Sources for Software-Controlled Devices

The PCM1862-Q1, PCM1863-Q1, PCM1864-Q1, and PCM1865-Q1 software-controlled devices support a wide

range of options for generating the clocks required to operate the ADC section, as well as an interface and other

control blocks, as shown in Figure 34.

The clocks for the PLL require a source reference clock. This clock source can be configured on software

devices as the XTAL, SCK or BCK.

These software-controlled devices share a similar clock tree for the generation and distribution of clocks, as

shown in Figure 33.

MUX for the incoming MCLK.

sources for the ADC, DSP1 and DSP2. These can mostly be ignored for the most common applications, but are

provided for advanced users.

mode BCK and LRCK will be a division of this. The selection is either SCKI/XTI or PLL. PLL can be used when

you have a non-audio rate reference clock (BCK or SCKI), as well as when you have an SCKI that is much too

slow for what is required for SCKO.

Most applications will use XTI/SCKI as the source for master mode SCK.

The CLKDET_EN (Page.0, 0x20) register bit (auto clock detector) is important; the clock detector is mainly

functional for slave modes, and for master modes where the master clock is a 256×, 384×, or 512× multiple of

the incoming data rate.

PCM1860 Datasheet(PDF) 36 Page - Texas Instruments

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