PCM1860 datasheet(8/141 Pages) TI1

8 / 141 page

PCM1860-Q1, PCM1861-Q1, PCM1862-Q1

PCM1863-Q1, PCM1864-Q1, PCM1865-Q1

SLASE64A – DECEMBER 2014 – REVISED JUNE 2017

www.ti.com

Product Folder Links: PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1

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(1)

Schmitt trigger input with internal pull-down (50 kΩ, typically).

Pin Functions: PCM1860-Q1 and PCM1861-Q1

TYPE

DESCRIPTION

NO.

NAME

VINL2/VIN1M

Analog input

Analog input 2, L-channel (or differential M input for input 1)

VINR2/VIN2M

Analog input

Analog input 2, R-channel (or differential M input for input 2)

VINL1/VIN1P

Analog input

Analog input 1, L-channel (or differential P input for input 1)

VINR1/VIN2P

Analog input

Analog input 1, R-channel (or differential P input for input 2)

Mic Bias

Power

Microphone bias output

VREF

Power

Reference voltage output decoupling point (typically, 0.5 AVDD). Connect 1-µF capacitor

from this pin to AGND.

AGND

Power

Analog ground

AVDD

Power

Analog power supply (typically, 3.3 V). Connect 0.1-µF and 10-µF capacitors from this pin

to AGND.

Digital output

Crystal oscillator output

Digital input

Crystal oscillator input or master clock input (1.8-V CMOS signal)

LDO

Power

Internal low-dropout regulator (LDO) decoupling output, or external 1.8-V input to bypass

LDO. Connect 0.1-µF and 10-µF capacitors from this pin to DGND.

DGND

Power

Digital ground

DVDD

Power

Digital power supply (typically, 3.3 V). Connect 0.1-µF and 10-µF capacitors from this pin to

DGND.

IOVDD

Power

Power supply for I/O voltages (typically, 3.3 V or 1.8 V).

SCKI

Digital input

CMOS level (3.3 V) master clock input

LRCK

Digital

input/output

Audio data word clock (left right clock) input/output(1)

BCK

Digital

input/output

Audio data bit clock input/output (1)

DOUT

Digital output

Audio data digital output

INT

Analog output

Interrupt output (for analog input detection). Pull high for active mode, pull low for idle.

MD6

Analog input

Analog MUX and gain selection using MD6, MD5, and MD2 pins, respectively:

000: SE Ch 1 (VINL1 and VINR1)

001: SE Ch 2 (VINL2 and VINR2)

010: SE Ch 3 (VINL3 and VINR3)

011: SE Ch 4 (VINL4 and VINR4)

100: SE Ch 4 with 12-dB gain

101: SE Ch 4 with 32-dB gain

110: Diff Ch 1 (VIN1P and VIN1M, VIN2P and VIN2M)

111: Diff Ch 2 (VIN3P and VIN3M, VIN4P and VIN4M) with 12-dB gain

MD5

Analog input

Analog MUX and gain selection (see MD6 pin for description)

MD4

Analog input

Audio format: high = left-justified, low = I2S

MD2

Analog input

Analog MUX and gain selection (see MD6 pin for description)

MD3

Digital Input

Filter select: 0 = FIR decimation filter, 1 = IIR low latency decimation filter

MD1

Analog input

Audio interface mode selection using MD1 and MD0 pins, respectively:

00: Slave mode, 256 × fS, 384 × fS, 512 × fS autodetect

01: Master mode (512 × fS)

10: Master mode (384 × fS)

11: Master mode (256 × fS)

MD0

Analog input

Audio interface mode selection (see MD1 pin for description)

VINL4/VIN4M

Analog input

Analog input 4, L-channel (or differential M input for input 4)

VINR4/VIN3M

Analog input

Analog input 4, R-channel (or differential M input for input 3)

VINL3/VIN4P

Analog input

Analog input 3, L-channel (or differential P input for input 4)

VINR3/VIN3P

Analog input

Analog input 3, R-channel (or differential P input for input 3)

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