FDC37C672 datasheet(88/173 Pages) SMSC

88 / 173 page

Enhanced Super I/O Controller with Fast IR

Datasheet

SMSC FDC37C672

Page 88

Rev. 10-29-03

DATASHEET

The bit map of the Extended Parallel Port registers is:

NOTE

data

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

ecpAFifo

Addr/RLE

Address or RLE field

Note

12.5

dsr

nBusy

nAck

PError

Select

nFault

Note

12.4

dcr

Direction

ackIntEn

SelectIn

nInit

autofd

strobe

Note

12.4

cFifo

Parallel Port Data FIFO

Note

12.5

ecpDFifo

ECP Data FIFO

Note

12.5

tFifo

Test FIFO

Note

12.5

cnfgA

cnfgB

compress

intrValue

Parallel Port IRQ

Parallel Port DMA

ecr

MODE

nErrIntrEn

dmaEn

serviceIntr

full

empty

Note 12.4 These registers are available in all modes.

Note 12.5 All FIFOs use one common 16 byte FIFO.

Note 12.6 The ECP Parallel Port Config Reg B reflects the IRQ and DRQ selected by the Configuration Registers.

12.3

ISA Implementation Standard

This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA

devices supporting ECP must meet the requirements contained in this section or the port will not be

supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended

Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993. This document is

available from Microsoft.

Description

The port is software and hardware compatible with existing parallel ports so that it may be used as a

standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of

gates to implement. It does not do any "protocol" negotiation, rather it provides an automatic high

burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions.

Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the

maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic

handshake for the standard parallel port to improve compatibility mode transfer speed.

The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is

accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the

next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte

the specified number of times. Hardware support for compression is optional.

FDC37C672 Datasheet(PDF) 88 Page - SMSC Corporation

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