AD9629 datasheet(21/33 Pages) AD

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AD9629

Data Sheet

Rev. B | Page 20 of 32

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9629 sample clock

inputs, CLK+ and CLK−, with a differential signal. The signal

is typically ac-coupled into the CLK+and CLK− pins via a

transformer or capacitors. These pins are biased internally (see

Figure 45) and require no external bias.

0.9V

AVDD

2pF

CLK–

CLK+

Figure 45. Equivalent Clock Input Circuit

Clock Input Options

The AD9629 has a very flexible clock input structure. The clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter is

of great concern,as described in the Jitter Considerations section.

Figure 46 and Figure 47 show two preferred methods for clock-

ing the AD9629. The CLK inputs supportup to 4× therated

sample rate when using the internal clockdivider feature.A low

jitter clock source is converted from a single-ended signal to a

differential signal using either an RF transformer or an RF balun.

0.1µF

SCHOTTKY

DIODES:

HSMS2822

CLOCK

INPUT

50Ω

100Ω

CLK–

CLK+

ADC

Mini-Circuits®

ADT1-1WT, 1:1 Z

XFMR

Figure 46. Transformer-Coupled Differential Clock (3 MHz to 200 MHz)

0.1µF

1nF

CLOCK

INPUT

1nF

50Ω

CLK–

CLK+

SCHOTTKY

DIODES:

HSMS2822

ADC

Figure 47. Balun-Coupled Differential Clock (Up to 4× Rated Sample Rate)

The RF balun configuration is recommended for clockfrequencies

between 80 MHzand 320 MHz,and the RF transformer is recom-

mended for clock frequencies from 3 MHz to 200 MHz. The

back-to-back Schottky diodes across the transformer/balun

secondary limit clock excursions into the AD9629 to ~0.8 V p-p

differential.

This limit helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9629 while

preserving the fast rise and fall times of the signal that are critical

to a low jitter performance.

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown in Figure 48. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516-4/AD9517-4 clock drivers

offer excellent jitter performance.

0Ω

0.1µF

240Ω

50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

ADC

AD951x

PECL DRIVER

Figure 48. Differential PECL Sample Clock (Up to 4× Rated Sample Rate)

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 49. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516-4/

AD9517-4 clock drivers offer excellent jitter performance.

0Ω

0.1µF

50kΩ

CLK–

CLK+

ADC

CLOCK

INPUT

CLOCK

INPUT

AD951x

LVDS DRIVER

Figure 49. Differential LVDS Sample Clock (Up to 4× Rated Sample Rate)

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended 1.8 V CMOS signal. In such

applications, drive the CLK+ pindirectlyfrom a CMOS gate, and

bypass the CLK− pin to ground with a 0.1 μF capacitor (see

Figure 50).

OPTIONAL

100Ω

0.1µF

50Ω1

50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

VCC

1kΩ

CLOCK

INPUT

AD951x

CMOS DRIVER

Figure 50. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

Input Clock Divider

The AD9629 contains an input clock divider with the ability

to divide the input clock by integer values of 1, 2, or 4.

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