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TMS320DM6431 Datasheet(PDF) 167 Page - Texas Instruments |
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TMS320DM6431 Datasheet(HTML) 167 Page - Texas Instruments |
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167 / 227 page ![]() DDR_CLK 1 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008 Table 6-27. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory Controller(1)(2)(see Figure 6-18) -3/-3Q/-3S NO. PARAMETER UNIT MIN MAX 1 tc(DDR_CLK) Cycle time, DDR_CLK 7.5 8 ns (1) DDR_CLK cycle time = 2 x PLL2 _SYSCLK1 cycle time. (2) The PLL2 Controller must be programmed such that the resulting DDR_CLK clock frequency is within the specified range. Figure 6-18. DDR2 Memory Controller Clock Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 167 |
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