TMS320DM6431 datasheet(170/227 Pages) TI1

170 / 227 page

6.10.1.2 VPFE Electrical Data/Timing

PCLK

TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Table 6-31. Timing Requirements for VPFE PCLK Master/Slave Mode(1) (see Figure 6-19)

-3/-3Q/-3S

NO.

UNIT

MIN

MAX

tc(PCLK)

Cycle time, PCLK

10.204

tw(PCLKH)

Pulse duration, PCLK high

0.4P

tw(PCLKL)

Pulse duration, PCLK low

0.4P

tt(PCLK)

Transition time, PCLK

(1)

P = PCLK period in ns.

Figure 6-19. VPFE PCLK Timing

Table 6-32. Timing Requirements for VPFE (CCD) Slave Mode(1) (see Figure 6-20)

-3/-3Q/-3S

NO.

UNIT

MIN

MAX

tsu(CCDV-PCLK)

Setup time, CCD valid before PCLK edge

4.5

th(PCLK-CCDV)

Hold time, CCD valid after PCLK edge

tsu(HDV-PCLK)

Setup time, HD valid before PCLK edge

4.5

th(PCLK-HDV)

Hold time, HD valid after PCLK edge

tsu(VDV-PCLK)

Setup time, VD valid before PCLK edge

4.5

th(PCLK-VDV)

Hold time, VD valid after PCLK edge

tsu(C_WEV-PCLK)

Setup time, C_WE valid before PCLK edge

4.5

th(PCLK-C_WEV)

Hold time, C_WE valid after PCLK edge

tsu(C_FIELDV-PCLK)

Setup time, C_FIELD valid before PCLK edge

4.5

th(PCLK-C_FIELDV)

Hold time, C_FIELD valid after PCLK edge

(1)

The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the

rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.

Peripheral Information and Electrical Specifications

170

Submit Documentation Feedback

TMS320DM6431 Datasheet(PDF) 170 Page - Texas Instruments

TMS320DM6431 Datasheet(HTML) 170 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL