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TMS320DM6431 Datasheet(PDF) 172 Page - Texas Instruments |
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TMS320DM6431 Datasheet(HTML) 172 Page - Texas Instruments |
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172 / 227 page  PCLK 18 20 22 HD VD C_FIELD TMS320DM6431 Digital Media Processor SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008 www.ti.com Table 6-34. Switching Characteristics Over Recommended Operating Conditions for VPFE (CCD) Master Mode(1) (see Figure 6-22) -3/-3Q/-3S NO. PARAMETER UNIT MIN MAX 18 td(PCLK-HDV) Delay time, PCLK edge to HD valid 2 9.5 ns 20 td(PCLK-VDV) Delay time, PCLK edge to VD valid 2 9.5 ns 22 td(PCLK-C_FIELDV) Delay time, PCLK edge to C_FIELD valid 2 9.5 ns (1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced. Figure 6-22. VPFE (CCD) Master Mode Control Output Data Timing 172 Peripheral Information and Electrical Specifications Submit Documentation Feedback |
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