500Msps, 8-Bit ADC with Track/Hold

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13

CLK and DCLK

All input and output clock signals are differential. The

input clocks, CLK and CLK, are the primary timing sig-

nals for the MAX101. CLK (pins 2, 62) and CLK (pins 3,

61) are fed to the internal circuitry through an internal

50

Ω transmission line. One set of CLK, CLK inputs

should be driven and the other pair terminated by 50

Ω

to -2V. Either set of inputs can be used as the driven

inputs (input lines are balanced) for easy circuit con-

CLK and CLK (Figures 1–3).

For best performance and consistent results, use a low-

phase-jitter clock source for CLK and CLK. Phase jitter

larger than 2ps from the input clock source reduces the

converter’s effective bits performance and causes

inconsistent results. The clock supplied to the MAX101

is internally divided by two, reshaped, and buffered.

This divided clock becomes the internal signal used as

strobes for the converters.

DCLK and DCLK are output clock signals derived from

the input clocks and are used for external timing of the

AData and BData outputs. (AData is valid after the ris-

ing edge of DCLK and BData is valid after the falling

edge.) They are fixed at one-half the rate of the input

clocks in normal mode (Table 1). The MAX101 is char-

acterized to work with 500MHz maximum input clock

frequencies. See

Typical Operating Circuit.

Output Mode Control (DIV10)

When DIV10 is grounded, it enables the test mode,

where the input incoming clock is divided by ten. This

reduces the output data and clock rates by a factor of

5, allowing the output clock duty cycle to remain at

50%. The clock to output phasing remains the same

and four out of every five sampled input values are dis-

carded.

When left open, this input (DIV10) is pulled low by inter-

nal circuitry and the converter functions in its normal

mode.

Layout, Grounding, and Power Supplies

A +5V ±5% supply as well as a -5.2V ±5% supply is

needed for proper operation. Bypass the VEE and VCC

supply pins to GND with high-quality 0.1µF and 0.001µF

ceramic capacitors located as close to the package as

possible. Connect all ground pins to a ground plane to

optimize noise immunity and highest device accuracy.

Phase Adjust

This control pin affects the point in time that one-half of

the converter samples the input signal relative to the

but can be adjusted over a ±1.25V range that typically

provides a ±18ps adjustment between the “A” side T/H

bridge strobe and the “B” side T/H bridge strobe.

Input Clock Phasing (TRK1, TRK1)

At power-up, the clock edge from which AData and

BData are synchronized is undetermined. The convert-

er can work from a specific input clock edge, as

described in the following paragraph.

TRK1 and TRK1 are differential inputs that are used in

addition to the normal input clock (CLK) to set data

phasing. A signal at one-half the input clock rate with

the proper setup and hold times (setup and hold typi-

cally 300ps) is applied to these inputs. Choose AData

by applying a logic “1” to TRK1 (“0” to TRK1) before

CLK’s negative transition. Choose BData by applying a

logic “0” at CLK’s negative edge (“1” to TRK1). In this

manner, several MAX101s can be interleaved to obtain

faster effective sampling rates. Voltages at the TRK1

input between ±50mV are interpreted as logic “1” and

voltages between -350mV and -500mV are interpreted

as logic “0”.