500Msps, 8-Bit ADC with Track/Hold

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7

______________________________________________________________Pin Description

32, 69, 80

VEE

31

DCLK

Complementary Differential Clock Outputs. Used to synchronize following circuitry: Outputs A0–A7

are valid after DCLK’s rising edge. B0–B7 output data are valid after DCLK’s falling edge (see Figure 1

for output timing information).

Negative Power Supply, -5.2V ±5% nominal

16, 48, 63

N.C.

35

10

“B” side negative reference voltage sense (Note 9)

DIV10

Divide by 10 mode. Leave open for normal operation. Selects test mode when grounded.

36, 38, 39,

41, 42, 44,

45, 47

A7–A0

29

SUB

No Connect—no internal connection to these pins.

12

TP3

5, 59

TRK1

Phasing inputs (normally left open). See

Applications Information section.

8, 21, 43,

56, 81

VCC

Positive Power Supply, +5V ±5% nominal

11

TP4

Internal connection, leave pin open.

13

“B” side positive reference voltage sense (Note 9)

9

“B” side negative reference voltage input (Note 9)

3, 61

CLK

Complementary Differential Clock Inputs. Can be driven from standard 10KH ECL with the following

considerations: Internally, pins 2, 62 and 3, 61 are the ends of a 50

Ω transmission line. Either end

can be driven with the other end terminated with 50

Ω to -2V. See Typical Operating Circuit.

4, 7, 15, 18,

24, 27, 30,

34, 37, 40,

46, 49, 57,

60, 64, 67,

68, 70, 71,

74, 77, 78,

79, 82, 84

GND

Power-Supply Ground

2, 62

CLK

NAME

FUNCTION

1

PAD

Internal connection, leave open.

PIN

14

“B” side positive reference voltage input (Note 9)

Internal connection, leave pin open.

33

DCLK

28, 26, 25,

23, 22, 20,

19, 17

B7–B0

AData and BData Outputs. A0 and B0 are the LSBs, and A7 and B7 are the MSBs. AData and BData

outputs conform to ECL logic swings and drive 100

Ω transmission lines. Terminate with 100Ω to -2V

(120

Ω for Tj > +100°C). See Figures 1–3.

6, 58

TRK1