500Msps, 8-Bit ADC with Track/Hold

4

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DIV10 = 0, Figures 1, 2

DIV10 = 0, Figures 1, 2

ns

CLK, CLK

CLK, CLK

0.7

1.3

1.8

DCLK to A/BData

Propagation Delay

DCLK

DATA

DCLK

DATA

20% to 80%

ps

700

ns

1.2

2.3

3.4

CLK to DCLK

Propagation Delay

CONDITIONS

See Figures 2, 3

and Table 1

20% to 80%

400

Clock

Cycles

Divide-by-1 mode

Pipeline Delay

(Latency)

15

15

ps

850

Fall Time

400

Rise Time

ns

0.9

2.5

ns

0.9

2.5

Clock Pulse Width Low

Clock Pulse Width High

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

TIMING CHARACTERISTICS

Note 3:

Note 4:

Deviation from best-fit straight line. See

Integral Nonlinearity section.

Note 5:

See the

Signal-to-Noise Ratio and Effective Bits section in the Detailed Description of Specifications.

Note 6:

SNR calculated from effective bits performance using the following equation: SNR(dB) = 1.76 + 6.02 x effective bits.

Note 7:

Note 8:

Outputs terminated through 100

Ω to -2.0V.

INTEGRAL NONLINEARITY

vs. OUTPUT CODE

-0.75

0.75

0

256

-0.50

0.50

OUTPUT CODE

64

192

128

0

-0.25

0.25

DIFFERENTIAL NONLINEARITY

vs. OUTPUT CODE

-0.75

0.75

0

256

-0.50

0.50

OUTPUT CODE

64

192

128

0

-0.25

0.25

__________________________________________Typical Operating Characteristics