DAC38RF82 datasheet(63/140 Pages) TI1

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D15

D14

D13

D12

D11

D10

Instruction Cycle

Data Transfer Cycle

td(Data)

SDEN\

SCLK

SDIO

SDEN\

SCLK

SDIO

SDO

D15

D14

D13

D12

D11

D10

SDO

Data n

Data n-1

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D15

D14

D13

D12

D11

D10

Instruction Cycle

Data Transfer Cycle

tS(SDEN\)

tS(SDIO) tH(SDIO)

tSCLK

SDEN\

SCLK

SDIO

SDEN\

SCLK

SDIO

DAC38RF82, DAC38RF89

www.ti.com

SLASEA6B – FEBRUARY 2017 – REVISED AUGUST 2017

Product Folder Links: DAC38RF82 DAC38RF89

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Figure 50 shows the serial interface timing diagram for a DAC38RF82 (or DAC38RF89) write operation. SCLK is

the serial interface clock input to DAC38RF82 (or DAC38RF89). Serial data enable SDEN is an active low input

to DAC38RF82 (or DAC38RF89). SDIO is serial data input. Input data to DAC38RF82 (or DAC38RF89) is

clocked on the rising edges of SCLK.

Figure 50. Serial Interface Write Timing Diagram

Figure 51 shows the serial interface timing diagram for a DAC38RF82 (or DAC38RF89) read operation. SCLK is

the serial interface clock input to DAC38RF82 (or DAC38RF89). Serial data enable SDEN is an active low input

to DAC38RF82 (or DAC38RF89). SDIO is serial data input during the instruction cycle. In 3 pin configuration,

SDIO is data out from the DAC38RF82 (or DAC38RF89) during the data transfer cycle, while SDO is in a high-

impedance state. In 4 pin configuration, both SDIO and SDO are data out from the DAC38RF82 (or

DAC38RF89) during the data transfer cycle. At the end of the data transfer, SDIO and SDO will output low on the

final falling edge of SCLK until the rising edge of SDEN when they will 3-state.

Figure 51. Serial Interface Read Timing Diagram

n the SIF interface there are four types of registers:

8.4.5.1 NORMAL (RW)

The NORMAL register type allows data to be written and read from. All 16-bits of the data are registered at the

same time. There is no synchronizing with an internal clock thus all register writes are asynchronous with respect

to internal clocks. There are three subtypes of NORMAL:

1. AUTOSYNC: A NORMAL register that causes a sync to be generated after the write is finished. These are

used when it is desirable to synchronize the block after writing the register or in the case of a single field that

spans across multiple registers. For instance, the NCO requires three 16-bit register writes to set the

frequency. Upon writing the last of these registers an autosync is generated to deliver the entire field to the

DAC38RF82 Datasheet(PDF) 63 Page - Texas Instruments

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