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S1740 Datasheet(PDF) 13 Page - Seiko Instruments Inc

Part # S1740
Description  POWER MONITORING OUTPUT, 5.5 V INPUT, 100 mA CMOS VOLTAGE REGULATOR WITH 0.5 uA SUPER LOW CURRENT CONSUMPTION
PDF  47 Pages
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Manufacturer  SII [Seiko Instruments Inc]
Direct Link  http://www.sii.co.jp
Logo SII - Seiko Instruments Inc

S1740 Datasheet(HTML) 13 Page - Seiko Instruments Inc

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POWER MONITORING OUTPUT, 5.5 V INPUT, 100 mA CMOS VOLTAGE REGULATOR WITH 0.5
μA SUPER LOW CURRENT CONSUMPTION
Rev.1.2_00
S-1740/1741 Series
13
Condition of Application
Input capacitor (CIN):
A ceramic capacitor with capacitance of 1.0
μF or more is recommended.
Output capacitor (CL):
A ceramic capacitor with capacitance of 1.0
μF to 100 μF is recommended.
Output capacitor (CPM):
A ceramic capacitor with capacitance of 100 nF to 220 nF is recommended.
Caution
Generally, in a voltage regulator, an oscillation may occur depending on the selection of the external
parts. Perform thorough evaluation including the temperature characteristics with an actual
application using the above capacitors to confirm no oscillation occurs.
Selection of Regulator Block Input Capacitor (CIN) and Output Capacitor (CL)
The S-1740/1741 Series requires CL between the VOUT pin and the VSS pin for regulator phase compensation.
The operation is stabilized by a ceramic capacitor with capacitance of 1.0
μF to 100 μF. When using an OS capacitor, a
tantalum capacitor or an aluminum electrolytic capacitor, the capacitance must also be 1.0
μF to 100 μF. However, an
oscillation may occur depending on the equivalent series resistance (ESR).
Moreover, the S-1740/1741 Series requires CIN between the VIN pin and the VSS pin for a stable operation.
Generally, an oscillaiton may occur when a voltage regulator is used under the conditon that the impedance of the power
supply is high. Note that the output voltage transient characteristics vary depending on the capacitance of CIN and CL and
the value of ESR.
Caution Perform thorough evaluation including the temperature characteristics with an actual application to
select CIN, CL.
Selection of Power Monitor Block Output Capacitor (CPM)
The S-1740/1741 Series requires CPM between the PMOUT pin and the VSS pin for power monitor phase compensation.
The operation is stabilized by a ceramic capacitor with capacitance of 100 nF to 220 nF. When using an OS capacitor, a
tantalum capacitor or an aluminum electrolytic capacitor, the capacitance must also be 100 nF to 220 nF. However, an
oscillation may occur depending on ESR.
Note that the output voltage transient characteristics vary depending on the capacitance of CPM and the value of ESR.
Caution Perform thorough evaluation including the temperature characteristics with an actual application to
select CPM.



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