MAX5477 datasheet(4/15 Pages) MAXIM

4 / 15 page

Dual, 256-Tap, Nonvolatile, I2C-Interface,

Digital Potentiometers

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Note 1:

All devices are production tested at TA = +25°C and are guaranteed by design and characterization for -40°C < TA < +85°C.

Note 2:

The DNL and INL are measured with the potentiometer configured as a voltage-divider with H_ = VDD and L_ = GND. The

wiper terminal is unloaded and measured with a high-input-impedance voltmeter.

Note 3:

The DNL and INL are measured with the potentiometer configured as a variable resistor. H_ is unconnected and L_ =

GND. For VDD = +5V, the wiper is driven with 400µA (MAX5477), 80µA (MAX5478), or 40µA (MAX5479). For VDD = +3V,

the wiper is driven with 200µA (MAX5477), 40µA (MAX5478), or 20µA (MAX5479).

Note 4:

The wiper resistance is measured using the source currents given in Note 3.

Note 5:

The devices draw current in excess of the specified supply current when the digital inputs are driven with voltages between

(VDD - 0.5V) and (GND + 0.5V). See Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics.

Note 6:

Wiper at midscale with a 10pF load (DC measurement). L_ = GND, an AC source is applied to H_, and the W_ output is

measured. A 3dB bandwidth occurs when the AC W_/H_ value is 3dB lower than the DC W_/H_ value.

Note 7:

The programming current exists only during power-up and EEPROM writes.

Note 8:

The SCL clock period includes rise and fall times (tR = tF). All digital input signals are specified with tR = tF = 2ns and

timed from a voltage level of (VIL + VIH) / 2.

Note 9:

Digital timing is guaranteed by design and characterization, and is not production tested.

Note 10: This is measured from the STOP pulse to the time it takes the output to reach 50% of the output step size (divider mode). It

is measured with a maximum external capacitive load of 10pF.

Note 11: An appropriate bus pullup resistance must be selected depending on board capacitance. Refer to the I

2C-bus specifica-

tion document linked to this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf

Note 12: The idle time begins from the initiation of the STOP pulse.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SCL High Time

tHIGH

0.6

µs

SCL Low Time

tLOW

1.3

µs

Data Setup Time

tSU:DAT

100

Data Hold Time

tHD:DAT

0.9

µs

SDA, SCL Rise Time

300

SDA, SCL Fall Time

300

Setup Time for STOP Condition

tSU:STO

0.6

µs

Bus Free Time Between STOP

and START Condition

tBUF

Minimum power-up rate = 0.2V/µs

1.3

µs

Pulse Width of Spike Suppressed

tSP

Capacitive Load for Each Bus

Line

(Note 11)

400

Write NV Register Busy Time

(Note 12)

TIMING CHARACTERISTICS (continued)

(VDD = +2.7V to +5.25V, H_ = VDD, L_ = GND, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +5V,

TA = +25°C. See Figure 1.) (Notes 8 and 9)

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