IC-GF datasheet(21/30 Pages) ICHAUS

21 / 30 page

iC-GF

TRANSCEIVER

Rev F1, Page 21/30

I(QPx)

texc

Iexc()

I(QNX)

QNx

QPx

ttrig

tdead

Isc()

Iexc()

Isc()

Figure 9: Dynamic characteristic

Feedback channel CFI–RX configuration

In SPI mode RX is a standard CMOS output, which can

also be configured as an open-drain output, using the

ENOD

Addr. 0x01; bit (0)

R/W 1

Push-pull output

Open-drain output

Table 15: RX configuration

The polarity of the feedback channel CFI–RX can be

configured using register bit POL (cf. Table 16). Pin

CFP has no function in SPI mode. The POL bit also

controls the pull-up/down current at CFI. The INVPUD

bit changes the polarity of the pull-up/down current at

CFI independent of the other configurations. The pul-

l-up/down current can be disconnected completely – if

required – by means of register bit ENPUD (cf. Table

17).

POL

Addr. 0x01; bit (2)

R/W 0

CFI hi → RX hi (ENOD = 0) resp. on (ENOD = 1)

Pull-down current (ENPUD = 1, INVPUD = 0)

CFI hi → RX lo (ENOD = 0) resp. off (ENOD = 1)

Pull-up current (ENPUD = 1, INVPUD = 0)

Table 16: Input polarity

ENPUD

Addr. 0x01; bit (3)

R/W 1

CFI pull-up/down disabled

CFI pull-up/down enabled

Table 17: Enable pull-up/down

The state of the CFI pin (high or low) is mapped inde-

pendent of POL to the register bit IND (see table 18).

Changes at CFI can be logged in the status bit CFED

(and signalled at pin NDIAG), if the bit ENCFD is set to

high. The CFED bit is cleared after read.

IND

Addr. 0x00; bit (7)

Input Signal at CFI is low

Input Signal at CFI is high

Table 18: CFI status

ENCFD

Addr. 0x02; bit (7)

R/W 0

CFED Disabled

CFED Enabled

Table 19: Enable edge detection at CFI

Table 20 summarizes the behaviour of the feedback

channel CFI in SPI mode.

Feedback channel CFI

CFI POL INVPUD IND RX (ENOD = 0) RX (ENOD = 1) Current at CFI

off

down

off

down

off

down

Table 20: Function table of feedback channel CFI in SPI mode (ENPUD = 1)

Overload detection

In SPI mode the counter decrements of the overload

detection can be programmed with the register DU-

TYC(1:0), resulting in different overload duty cycles at

the switching channels. The maximum allowed over-

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