GF9101 datasheet(13/23 Pages) ETC

13 / 23 page

520 - 64 - 7

For the 48 tap filter, input data A n and coefficients C n are

shown in Figure 12. The pipelined output section of the 48

tap filter is shown in Figure 14. Note that two register delays

are introduced due to R2 and R3 between the accumulators

of device number 1 and number 2. An additional delay is

introduced when the filter-sum is fed back to be added to

the next sum by selecting FB_SEL_1. The timing diagram

for the 48 tap asymmetric filter is shown in Figure 15. The

processing clock runs at twice the data rate since the A and

B registers of the GF9101 are multiplexed internally..

Fig. 12 Input Data An and Coefficients Cn

TABLE 11 Configuration Word for the Cascaded GF9101’s

DEVICE NO. 1

DEVICE NO. 2

BIT NO.

CONFIG.

WORD

CONFIG.

WORD

DESCRIPTION

Data A and B are both signed data.

1 clock cycle delay in device no. 1 and 4 clock delay in device no. 2

Using each device as 2 x 12 tap filters. Note that in device no. 2

DATA_A_OUT is externally connected to DATA_B_IN.

Assuming serial load mode selected for both devices.

C36

C38

C40

C41

C44

C43

C39

C42

C45 C46

C37

C47

A47

A11

A45

A40

A41

A42

A43

A46

A10

A44

GF9101 Datasheet(PDF) 13 Page - List of Unclassifed Manufacturers

GF9101 Datasheet(HTML) 13 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL