LTC4211CS8 datasheet(15/36 Pages) LINER

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LTC4211

4211f

a start-up check to make sure the supply voltage is above

its 2.3V UVLO threshold (see Time Point 1). If the input

supply voltage is valid, the gate of the external pass

transistor is pulled to ground by the internal 200

µAcurrent

source connected at the GATE pin. The TIMER pin is held

low by an internal N-channel pull-down transistor (see

M6, LTC4211 Block Diagram) and the FILTER pin voltage

is pulled to ground by an internal 10

µA current source.

Once VCC and ON (the ON pin is >1.316) are valid, the

LTC4211 checks to make sure that GATE is OFF (VGATE <

0.2V) at Time Point 2. An internal timing circuit is enabled

and the TIMER pin voltage ramps up at the rate described

by Equation 1. At Time Point 3 (the timing period pro-

grammed by CTIMER), the TIMER pin voltage equals VTMR

(1.236V). Next, the TIMER pin voltage ramps down to

Time Point 4 where the LTC4211 performs two checks: (1)

FILTER pin voltage is low (VFILTER < 1.156V) and (2)

FAULT pin voltage is high (VFAULT > 1.286V). If both

conditions are met, the LTC4211 begins a second timing

(soft-start) cycle.

Second Timing (Soft-Start) Cycle

At the beginning of the second timing cycle (Time Point 5),

the LTC4211’s FAST COMP is armed and an internal 10

µA

current source working with an internal charge pump

provides the gate drive to the external pass transistor. An

expression for the GATE voltage slew rate is given by

Equation 3:

Slew Rate

GATE

(3)

where CGATE = Power MOSFET gate input capacitance

(CISS).

For example, a Si4410DY (a 30V N-channel power MOSFET)

exhibits an approximate CGATE of 3300pF at VGS = 10V. The

LTC4211’s GATE voltage rate-of-change (slew rate) for

this example would be:

Slew Rate

GATE

3300

303

The inrush current being delivered to the load while the

GATE is ramping is dependent on CLOAD and CGATE.

Equation 4 gives an expression for the inrush current

during the second timing cycle:

INRUSH

GATE

LOAD

GATE

== µ

••

(4)

For example, if CGATE = 3300pF and CLOAD = 2000µF, the

inrush current charging CLOAD is:

INRUSH =µ

2000

0 0033

606

•

(5)

At Time Point 6, the output voltage trips COMP2’s thresh-

old, signaling an output voltage “power good” condition.

At Time Point 7, RESET is asserted high, SLOW COMP is

armed and the LTC4211 enters a fault monitor mode. The

TIMER voltage then ramps down to Time Point 8.

Power-Off Cycle

As shown at Time Point 9, an external hard reset is initiated

by pulling the ON pin low (VON < 1.236V). The GATE pin

voltage is ramped to ground by the internal 200

µA current

source, discharging CGATE and turning off the pass tran-

sistor. As CLOAD discharges, the output voltage crosses

COMP2’s threshold, signaling a “power bad” condition at

Time Point 10. At this point, RESET is asserted low.

SOFT-START WITH CURRENT LIMITING

During the second timing cycle, the inrush current was

described by Equation 4. Note that there is a one-to-one

correspondence in the inrush current to CLOAD. If the

inrush current is large enough to cause a voltage drop

greater than 50mV across the sense resistor, an internal

servo loop controls the operation of the 10

µA current

source at the GATE pin to regulate the load current to:

LIMIT SOFTSTART

SENSE

() =

(6)

For example, the inrush current is limited to 5A when

RSENSE = 0.01Ω.

OPERATIO

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