LTC4211CS8 datasheet(31/36 Pages) LINER

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LTC4211

4211f

FAULT is asserted low (but not latched) to indicate a start-

up failure. Only if the input overvoltage condition is re-

moved before Time Point 5 does the start-up sequence

resume at the second timing cycle. At this point in time, the

GATE pin voltage is allowed to ramp up, FAULT is pulled

to logic high and the circuit breaker is armed. Should, at

any time after Time Point 5, a supply overvoltage condition

develop (VFILTER > 1.236V), the electronic circuit breaker

will trip, the GATE will be pulled low to turn off the external

MOSFET and FAULT will be asserted low and latched. This

sequence is shown in detail at Time Point B.

APPLICATIO S I FOR ATIO

Low Side (Output) Overvoltage Protection

A Zener diode can be used in a similar fashion to detect/

protect the system against a supply overvoltage condition

on the load (or low) side of the pass transistor. In this case,

the Zener diode is connected from the load to the LTC4211’s

FILTER pin, as shown in Figure 25. An additional diode,

D1, prevents the FILTER pin from pulling low during an

output short-circuit. Figure 26 illustrates the timing dia-

gram for a low side output overvoltage condition. In this

example, the LTC4211 can only sense the overvoltage

supply condition after Time Point 5 and the GATE pin has

Figure 24. High Side Overvoltage Protection

VCC

TIMER

GATE

RESET

FILTER

>VREF – 80mV

FAULT

VOUT

GATE

VOUT

A B C

SLOW COMPARATOR ARMED

IF OVERVOLTAGE GOES

AWAY, SECOND CYCLE

CONTINUES

OVERVOLTAGE

IF ANY FAULT HAPPENS

AFTER THIS POINT, THE

CIRCUIT BREAKER TRIPS

AND FAULT LATCHES LOW

OVERVOLTAGE CIRCUIT BREAKER

TRIPS, GATE PULLS DOWN AND

FAULT LATCHES LOW

FAULT IS PULLED LOW (BUT NOT LATCHED)

DUE TO A START-UP OVERVOLTAGE PROBLEM

POWER GOOD

VFB > VREF

POWER BAD

VFB < VREF

FPD

4211 F24

>VREF

FAULT

LATCHED LOW

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