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LTC4211CS8 Datasheet(PDF) 28 Page - Linear Technology |
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LTC4211CS8 Datasheet(HTML) 28 Page - Linear Technology |
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28 / 36 page ![]() 28 LTC4211 4211f APPLICATIO S I FOR ATIO voltage side of the MOSFET switch. An abrupt connection, produced by inserting the board into a backplane connec- tor, resulting in a fast rising edge applied on the supply line of the LTC4211. Since there is no bulk capacitance to damp the parasitic track inductance, supply voltage transients excite parasitic resonant circuits formed by the power MOSFET capacitance and the combined parasitic inductance from the wiring harness, the backplane and the circuit board traces. In these applications, there are two methods that should be applied together for eliminating these supply voltage transients: using transient voltage suppressor to clip the transient to a safe level and snubber networks. Snubber networks are series RC networks whose time constants are experimentally determined based on the board’s para- sitic resonance circuits. As a starting point, the capacitors in these networks are chosen to be 10 × to 100× the power MOSFET’s COSS under bias. The series resistor is a value determined experimentally and ranges from 1 Ω to 50Ω, depending on the parasitic resonance circuit. For applica- tions with supply voltages of 12V or higher the ringing and overshoot during hot-swapping or when the output is short-circuited can easily exceed the absolute maximum specification of the LTC4211. To reduce the danger, transient voltage suppressors and snubber networks are highly recommended. For applications with lower supply voltage such as 5V, usually a snubber is adequate to reduce the supply ringing. Although, the need of a tran- sient voltage suppressor arises for inductive and high current application. Note that in all LTC4211 5V applica- tions schematics, transient suppressor and snubber net- works have been added for protection. The transient suppressor is optional and a simple short-circuit test can be performed to determine the need of it. These protection networks should be mounted very close to the LTC4211’s supply input rail using short lead lengths to minimize lead inductance. This is shown schematically in Figure 21, and a recommended layout of the transient protection devices around the LTC4211 is shown in Figure 22. 1 2 3 4 8 7 6 5 VCC SENSE GATE FB RESET ON TIMER GND LTC4211 4211 F20 D1 1N4148 D2 1N4148 Q1 1/2 Si4936DY Q2 1/2 Si4936DY R2 0.015 Ω 5% R3 10 Ω 5% R8 10 Ω Z1* C4 0.1 µF C1 10nF 16V R1 10k 5% R6 1M 5% R7 10 Ω 5% R4 2.74k 1% TRIP POINT: 4.06V R5 1.2k 1% C3 0.047 µF 25V C2 0.022 µF 25V CLOAD CLOAD D3** VOUT1 3.3V 2A VOUT2 5V 2A 5V OUT 3.3V OUT CURRENT LIMIT: 3.3A + + R9 10 Ω R10 10k 10k Z2* C5 0.1 µF R11 10k LONG 3.3V GND RESET LONG **D3 IS OPTIONAL AND HELPS DISCHARGE VOUT1 IF VOUT2 SHORTS PCB EDGE CONNECTOR (MALE) LONG BACKPLANE CONNECTOR (FEMALE) 5V SHORT SHORT ON Z1, Z2: 1SMA10A OR SMAJ10A * OPTIONAL Figure 20. Switching 5V and 3.3V Figure 21. Placing Transient Protection Devices Close to the LTC4211’s Input Rail + VCC SENSE LTC4211 8 3 4 76 COUT VOUT 5V 5A OUTPUT GND INPUT GND 4211 F21 5 1 2 R2 15k GATE GND TIMER CTIMER FB ON ON RESET RX 10 Ω VIN 5V RSENSE 0.007 Ω Q1 Si4410DY R1 36k RESET Z1* CX 0.1 µF Z1 = 1SMA10A OR SMAJ10A * OPTIONAL |
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