LTC4211CS8 datasheet(33/36 Pages) LINER

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LTC4211

4211f

APPLICATIO S I FOR ATIO

ramped up to its nominal operating value. After Time

Point 5, a supply voltage fault occurs at the load and the

Zener diode begins to conduct, causing VFILTER to in-

crease. At Time Point 6A, VFILTER is greater than 1.236V,

the circuit breaker is tripped, the GATE pin voltage is pulled

to ground and FAULT is asserted low and latched.

In either case, the LTC4211 can be configured to auto-

matically initiate a start-up sequence. Please refer to the

section on AutoRetry After a Fault for additional

information.

PCB Layout Considerations

For proper operation of the LTC4211’s circuit breaker

function, a 4-wire Kelvin connection to the sense resistors

is highly recommended. A recommended PCB layout for

the sense resistor, the power MOSFET and the GATE drive

components around the LTC4211 is illustrated in

Figure 22. In Hot Swap applications where load currents

can reach 10A or more, narrow PCB tracks exhibit more

resistance than wider tracks and operate at more elevated

temperatures. Since the sheet resistance of 1 ounce cop-

per foil is approximately 0.54m

Ω/square, track resis-

tances add up quickly in high current applications. Thus,

to keep PCB track resistance and temperature rise to a

minimum, PCB track width must be appropriately sized.

Consult Appendix A of LTC Application Note 69 for details

on sizing and calculating trace resistances as a function of

copper thickness.

In the majority of applications, it will be necessary to use

plated-through vias to make circuit connections from

component layers to power and ground layers internal to

the PC board. For 1 ounce copper foil plating, a good

starting point is 1A of DC current per via, making sure the

via is properly dimensioned so that solder completely fills

any void. For other plating thicknesses, check with your

PCB fabrication facility.

LTC4211CS8 Datasheet(PDF) 33 Page - Linear Technology