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LTC4211CS8 Datasheet(PDF) 24 Page - Linear Technology |
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LTC4211CS8 Datasheet(HTML) 24 Page - Linear Technology |
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24 / 36 page ![]() 24 LTC4211 4211f APPLICATIO S I FOR ATIO A more elaborate connection sense scheme is shown in Figure 16. The bases of Q1 and Q2 are wired to short pins located on opposite ends of the edge connector because the installation/removal of printed circuit cards generally requires rocking the card back and forth. When VCC makes connection, the bases of transistors Q1 and Q2 are pulled high, biasing them ON. When either one of them is ON, the LTC4211’s ON pin is held low, keeping the LTC4211 OFF. When both the short base connector pins + VCC RESET SENSE ON R5 15k LTC4211 GATE FB 8 7 6 5 4211 F13 1 2 4 3 CTIMER 10nF GND TIMER R4 36k VOUT 5V 5A Q1 Si4410DY RSENSE 0.007 Ω COUT R6 10k Z1* Z1 = 1SMA10A OR SMAJ10A * OPTIONAL R1 10 Ω C1 0.1 µF R2 10k VIN 5V SHORT LONG 5V VCC RESET LONG PCB EDGE CONNECTOR (MALE) SHORT BACKPLANE CONNECTOR (FEMALE) + VCC SENSE ON R2 100k RESET LTC4211 GATE FB 7 8 6 1 5 Z1 = 1SMA10A OR SMAJ10A * OPTIONAL 4211 F14 2 4 3 CTIMER 10nF R3 10k GND TIMER RESET VOUT 5V 5A Q1 Si4410DY RSENSE 0.007 Ω COUT R1 36k R4 10k R5 10k PCB CONNECTION SENSE RX 10 Ω CX 0.1 µF Z1* VIN 5V SHORT LONG SHORT PCB EDGE CONNECTOR (MALE) LONG SHORT BACKPLANE CONNECTOR (FEMALE) Q2 R7 15k Figure 13. Hot Swap Controller On Daughter Board (Staggered Pin Connections) Figure 14. Hot Swap Controller on Backplane (Staggered Pin Connections) of Q1 and Q2 finally mate to the backplane, their bases are grounded, biasing the transistors OFF. The ON pin volt- age is then pulled high by R3 enabling the LTC4211 and a power-up cycle begins. A software-initiated power-down cycle can be started by momentarily driving transistor M1 with a logic high signal. This in turn will drive the LTC4211’s ON pin low. If the ON pin is held low for more than 8 µs, the LTC4211’s GATE pin is switched to ground. |
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