AD7617BSTZ datasheet(32/52 Pages) AD

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Data Sheet

AD7617

Rev. 0 | Page 31 of 51

DIGITAL INTERFACE

CHANNEL SELECTION

Hardware Mode

The logic level of the CHSELx signals determine the channel pair

for conversion; see Table 14 for signal decoding information. The

CHSELx signals at the time that either full or partial reset is

released determine the initial channel pair to sample. After a reset,

the logic levels of the CHSELx signals are examined during the

BUSY high period to set the channel pair for the next conversion.

The CHSELx signal level must be set before CONVST goes from

low to high and be maintained until BUSY goes from high to low

to indicate a conversion is complete. See Figure 52 for

further details.

Software Mode

In software mode, the channels for conversion are selected by

control of the channel register. On power-up or after a reset, the

default channels selected for conversion are Channel V0A and

Channel V0B (see Figure 53).

Table 14. CHSELx Pin Decoding

Channel Selection Input Pin

Analog Input Channels for

Conversion

CHSEL0

CHSEL1

CHSEL2

V0A, V0B

V1A, V1B

V2A, V2B

V3A, V3B

V4A, V4B

V5A, V5B

V6A, V6B

V7A, V7B

Figure 52. Hardware Mode Channel Conversion Setting

Figure 53. Software Serial Mode Channel Conversion Setting

RESET

CONVST

BUSY

CHx

A/Bx

A/By

A/Bz

CHy

CHz

CH...

CHSEL2

CHSEL0

DATA BUS

CONFIGURE POINT

INITIAL SETUP

RESET

CONVST

BUSY

WRITE CHx

WRITE CHy

WRITE CHz

WRITE CH...

SDI

A/B0

A/Bx

A/By

SDOA,

SDOB

CHx CONVERSION START

DO NOT CARE

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