AD7617BSTZ datasheet(33/52 Pages) AD

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AD7617

Data Sheet

Rev. 0 | Page 32 of 51

Figure 54. Software Parallel Mode Channel Conversion Setting

PARALLEL INTERFACE

The parallel interface reads the conversion results, and config-

ures and reads back the on-chip registers. Data can be read from

the AD7617 via the parallel data bus with standard CS, RD,

and WR signals. To read the data over the parallel bus, tie the

SER/PAR pin low.

Reading Conversion Results

The CONVST signal initiates the conversion process. A low to

high transition on the CONVST signal initiates a conversion of

the selected inputs. The BUSY signal goes high to indicate a

conversion is in progress. When the BUSY signal transitions

from high to low to indicate that a conversion is complete, it is

possible to read back conversion results on the parallel interface.

Data can be read from the AD7617 via the parallel data bus with

standard CS and RD signals. The CS and RD input signals are

internally gated to enable the conversion result onto the data

bus. The data lines, DB15 to DB2, leave their high impedance

state when both CS and RD are logic low. DB15 is the MSB of

the conversion result and DB2 is the LSB of the 14-bit conversion

result. The data lines DB1 and DB0 are only used for register

write/read operations or for reading the CRC result.

The rising edge of the CS input signal three-states the bus, and

the falling edge of the CS input signal takes the bus out of the

high impedance state. CS is the control signal that enables the

data lines; it is the function that allows multiple AD7617

devices to share the same parallel data bus.

The number of required read operations depends on the device

configuration. A minimum of two reads are required to read the

conversion result for the simultaneously sampled A and B channels.

If additional functions such as CRC, status, and burst mode are

enabled, the number of required readbacks increases accordingly.

The RD pin reads data from the output conversion results register.

Applying a sequence of RD pulses to the RD pin of the AD7617

clocks the conversion results out from each channel onto the

parallel bus, DB15 to DB2.

The first RD falling edge after BUSY goes low clocks out the

conversion result from Channel AX. The next RD falling edge

updates the bus with the Channel BX conversion result.

Writing Register Data

In software mode, all the read/write registers in the AD7617

may be written to over the parallel interface. A register write

command is performed by a single 16-bit parallel access via the

parallel bus (DB15 to DB0), CS, and WR signals. Provide data

written to the AD7617 on the DB15 to DB0 inputs, with DB0

being the LSB of the data-word. The format for a write command

is shown in Figure 55. Bit D15 must be set to 1 to select a write

command. Bits[D14:D9] contain the register address. The

subsequent nine bits (Bits[D8:D0]) contain the data to be

written to the selected register. See the Register Summary

section for the complete list of register addresses. Data is

latched into the device on the rising edge of WR.

Figure 55. Parallel Interface Register Write

Reading Register Data

All the registers in the device can be read over the parallel interface.

A register read is performed by first writing the address of the

command is shown in Figure 57. Bit D15 must be set to 0 to

select a read command. Bits[D14:D9] contain the register address.

The subsequent nine bits (Bits[D8:D0]) are ignored. The read

command is latched into the AD7617 on the rising edge of WR.

This latch transfers the relevant register data to the output register.

The register data can then be read on the DB15 to DB0 pins by

using a standard read command. See Figure 57 for additional

information.

RESET

CONVST

BUSY

CHx

B0 CHy

Bx CHz

By CH

DB0 TO

DB15

CHx CONVERSION START

WRITE REG 1

WRITE REG 2

DB15

DB0

AD7617BSTZ Datasheet(PDF) 33 Page - Analog Devices

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