AD7617BSTZ datasheet(30/52 Pages) AD

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Data Sheet

AD7617

Rev. 0 | Page 29 of 51

Table 12. Summary of Latched Hardware Signals1

Signal

Latched at Full Reset

Read at Reset

Read During Busy

Edge Driven

HW Mode

SW Mode

Mode

REFSEL

Yes

SEQEN

Yes

HW_RNGSELx (Range Change)

Yes

HW_RNGSELx (Hardware (HW) or Software

(SW) Mode)

Yes

SER/PAR

Yes

CRCEN

Yes

OSx

Yes

BURST

Yes

CHSELx

Yes

SER1W

Yes

Blank cells in Table 12 mean not applicable.

SOFTWARE MODE

If software mode is selected and the reference and interface type

is configured, all other configuration settings in the AD7617 are

controlled via the on-chip registers. All functionality of the AD7617

is available when software mode is selected. Table 12 provides a

summary of the signals that are latched by the device on the release

of a full reset, depending on the mode of operation chosen.

RESET FUNCTIONALITY

The AD7617 has two reset modes: full or partial. The reset mode

selected is dependent on the length of the reset low pulse. A partial

reset requires the RESET pin to be held low between 40 ns and

500 ns. After 50 ns from release of RESET, the device is fully

functional and a conversion can initiate. A full reset requires

the RESET pin to be held low for a minimum of 1.2 µs. After

15 ms from release of RESET, the devices is completely

reconfigured and a conversion can initiate.

A partial reset reinitializes the following modules:

•

Sequencer

•

Digital filter

•

SPI

•

Both SAR ADCs

The current conversion result is discarded on completion of a

partial reset. The partial reset does not affect the register values

programmed in software mode or the latches that store the user

configuration in both hardware and software modes. A dummy

conversion is required in software mode after a partial reset.

A full reset returns the device to its default power-on state. The

following features are configured when the AD7617 is released

from full reset:

•

Hardware mode or software mode

•

Internal/external reference

•

Interface type

On power-up, the RESET signal can be released as soon as both

the VCC and VDRIVE supplies are stable. The logic level of the

HW_RNGSELx, REFSEL, SER/PAR and DB4/SER1W pins when

the RESET pin is released after a full reset determines the

configuration.

If hardware mode is selected, the functionality determined by

the CRC, BURSTEN, SEQEN, and OSx signals is also latched

when the RESET pin transitions from low to high in full reset

mode. After the functionality is configured, changes to these

signals are ignored. In hardware mode, the analog input range

(HW_RNGSELx signals) can be configured during either a full

or partial reset or during normal operation; however, hardware/

software mode selection requires a full reset to reconfigure

while this setting is latched.

In hardware mode, the CHSELx and HW_RNGSELx pins are

queried at release from both a full and a partial reset to perform

the following actions:

•

Determine the initial analog input channel pair to acquire

for conversion.

•

Configure the initial settings for the sequencer.

•

Select the analog input voltage range.

The CHSELx and HW_RNGSELx signals are not latched. The

channel pair selected for conversion, or the hardware sequencer,

can be reconfigured during normal operation by setting and

maintaining the CHSELx signal level before the CONVST rising

edge, and ensuring the signal level remains constant until after

BUSY transitions low again. See the Channel Selection section

for further details.

In software mode, all additional functionality is configured by

controlling the on-chip registers.

AD7617BSTZ Datasheet(PDF) 30 Page - Analog Devices

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