AD7617BSTZ datasheet(14/52 Pages) AD

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Data Sheet

AD7617

Rev. 0 | Page 13 of 51

Pin No.

Type1

Mnemonic2

Description

DO/DI

DB4/SER1W

Parallel Output/Input Data Bit 4/Serial Output Selection. In parallel mode, this pin acts as a

three-state parallel digital output/input pin. Refer to the Parallel Interface section for further

details.

In serial mode, this pin determines whether the serial output operates over SDOA and SDOB

or just SDOA. When SER1W is low, the serial output operates over SDOA only. When SER1W is

high, the serial output operates over both SDOA and SDOB. The signal state is latched on the

release of a full reset, and requires an additional full reset to reconfigure.

DO/DI

DB5/CRCEN

Parallel Output/Input Data Bit 5/Cyclic Redundancy Check (CRC) Enable Input. In parallel

mode, this pin acts as a three-state parallel digital input/output. While in serial mode, this pin

acts as a CRC enable input. The CRCEN signal state is latched on the release of a full reset, and

requires an additional full reset to reconfigure. Refer to the Digital Interface section for further

details.

In serial mode, when CRCEN is low, there is no CRC word following the conversion results;

when CRCEN is high, an extra CRC word follows the last conversion word configured by

CHSELx. See the CRC section for further details.

In software mode, this pin must be connected to DGND.

47, 48

DO/DI

DB6, DB7

Parallel Output/Input Data Bit 6 and Data Bit 7. When SER/PAR = 0, these pins act as three-

state parallel digital input/outputs. Refer to the Parallel Interface section for further details. In

serial mode, when SER/PAR = 1, these pins must be tied to DGND.

VDRIVE

Logic Power Supply Input. The voltage (2.3 V to 3.6 V) supplied at this pin determines the

operating voltage of the interface. This pin is nominally at the same supply as the supply of

the host interface. Decouple this pin with 0.1 µF and 10 µF capacitors in parallel.

GND

DGND

Digital Ground. This pin is the ground reference point for all digital circuitry on the AD7617.

The DGND pin must connect to the DGND plane of a system.

CAP

REGGNDD

Ground for the Digital Low Dropout (LDO) Regulator Connected to REGCAPD (Pin 52).

CAP

REGCAPD

Decoupling Capacitor Pin for Voltage Output from Internal Digital Regulator. Decouple this

output pin separately to REGGNDD using a 10 μF capacitor. The voltage at this pin is 1.89 V typical.

53, 54

DO/DI

DB8, DB9

Parallel Output/Input Data Bit 9 and Data Bit 8. When SER/PAR = 0, these pins act as three-

state parallel digital input/outputs. Refer to the Parallel Interface section for further details.

In serial mode, when SER/PAR = 1, these pins must be tied to DGND.

DO/DI

DB10/SDI

Parallel Output/Input Data Bit DB10/Serial Data Input. When SER/PAR = 0, this pin acts as a

three-state parallel digital input/output. Refer to the Parallel Interface section for further

details. In hardware serial mode, tie this pin to DGND.

In serial mode, when SER/PAR = 1, this pin acts as the data input of the SPI interface.

DO/DI

DB11/SDOB

Parallel Output/Input Data Bit 11/Serial Data Output B. When SER/PAR = 0, this pin acts as a

three-state parallel digital input/output. Refer to the Parallel Interface section for further

details.

In serial mode, when SER/PAR = 1 and DB4/SER1W = 1, this pin functions as SDOB and outputs

serial conversion data.

DO/DI

DB12/SDOA

Parallel Output/Input Data Bit 12/Serial Data Output A. When SER/PAR = 0, this pin acts as a

three-state parallel digital input/output. Refer to the Parallel Interface section for further

details.

In serial mode, when SER/PAR = 1, this pin functions as SDOA and outputs serial conversion data.

58, 59, 60

DO/DI

DB13/OS0,

DB14/OS1,

DB15/OS2

Parallel Output/Input Data Bit 13, Data Bit 14, and Data Bit 15/Oversampling Ratio Selection.

When SER/PAR = 0, these pins act as three-state parallel digital input/outputs. Refer to the

Parallel Interface section for further details.

In serial hardware mode, these pins control the oversampling settings. The signal state is

latched on the release of a full reset and requires an additional full reset to reconfigure. See the

Digital Filter section for further details.

In software serial mode, these pins must be connected to DGND.

WR/BURST

Write/Burst Mode Enable.

In software parallel mode, this pin acts as WR for a parallel interface.

In hardware parallel or serial mode, this pin enables BURST mode. The signal state is latched on

the release of a full reset, and requires an additional full reset to reconfigure. Refer to the Burst

Sequencer section for further information.

In software serial mode, connect this pin to DGND.

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