AD9691 datasheet(4/73 Pages) AD

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Data Sheet

AD9691

Rev. 0 | Page 3 of 72

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified

maximum sampling rate (1250 MSPS), 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, clock divider = 2, default SPI settings,

TA = 25°C, unless otherwise noted.

Table 1.

Parameter

Temperature

Min

Typ

Max

Unit

RESOLUTION

Full

Bits

ACCURACY

No Missing Codes

Full

Guaranteed

Offset Error

Full

−0.31

+0.31

% FSR

Offset Matching

Full

0.3

% FSR

Gain Error

Full

−6

% FSR

Gain Matching

Full

3.9

% FSR

Differential Nonlinearity (DNL)

Full

−0.8

±0.5

+0.8

LSB

Integral Nonlinearity (INL)

Full

−6.5

±2.6

+6.5

LSB

TEMPERATURE DRIFT

Offset Error

25°C

−26

ppm/

°C

Gain Error

25°C

±9.8

ppm/

°C

INTERNAL VOLTAGE REFERENCE

Voltage

Full

1.0

INPUT REFERRED NOISE

VREF = 1.0 V

25°C

3.53

LSB rms

ANALOG INPUTS

Differential Input Voltage Range

Full

1.58

V p-p

Common-Mode Voltage (VCM)

25°C

2.05

Differential Input Capacitance

25°C

1.5

Analog Input Full Power Bandwidth

25°C

GHz

POWER SUPPLY

AVDD1

Full

1.22

1.25

1.28

AVDD2

Full

2.44

2.50

2.56

AVDD3

Full

3.2

3.3

3.4

AVDD1_SR

Full

1.22

1.25

1.28

DVDD

Full

1.22

1.25

1.28

DRVDD

Full

1.22

1.25

1.28

SPIVDD

Full

1.7

1.8

3.4

IAVDD1

Full

800

840

IAVDD2

Full

670

770

IAVDD3

Full

125

140

IAVDD1_SR

Full

IDVDD1

Full

250

290

IDRVDD2

Full

310

380

ISPIVDD

Full

POWER CONSUMPTION

Total Power Dissipation (Including Output Drivers)1

Full

3.8

Power-Down Dissipation

Full

0.9

Standby3

Full

1.5

Default mode. No DDCs used. L = 8, M = 2, and F = 1.

All lanes running. Power dissipation on DRVDD changes with the lane rate and number of lanes used.

Standby mode can be controlled by the SPI.

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