AD9691 datasheet(12/73 Pages) AD

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Data Sheet

AD9691

Rev. 0 | Page 11 of 72

Pin No.

Mnemonic

Type

Description

CMOS Outputs

21, 46

FD_A, FD_B

Output

Fast Detect Outputs for Channel A and Channel B, respectively.

Digital Inputs

25, 26

SYNCINB−, SYNCINB+

Input

Active Low JESD204B LVDS Sync Input Complement/True.

79, 80

SYSREF+, SYSREF−

Input

Active Low JESD204B LVDS System Reference Input

True/Complement.

Data Outputs

27, 28

SERDOUT0−, SERDOUT0+

Output

Lane 0 Output Data Complement/True.

29, 30

SERDOUT1−, SERDOUT1+

Output

Lane 1 Output Data Complement/True.

31, 32

SERDOUT2−, SERDOUT2+

Output

Lane 2 Output Data Complement/True.

33, 34

SERDOUT3−, SERDOUT3+

Output

Lane 3 Output Data Complement/True.

35, 36

SERDOUT4−, SERDOUT4+

Output

Lane 4 Output Data Complement/True.

37, 38

SERDOUT5−, SERDOUT5+

Output

Lane 5 Output Data Complement/True.

39, 40

SERDOUT6−, SERDOUT6+

Output

Lane 6 Output Data Complement/True.

41, 42

SERDOUT7−, SERDOUT7+

Output

Lane 7 Output Data Complement/True.

Device Under Test (DUT)

Controls

PDWN/STBY

Input

Power-Down Input (Active High). The operation of this pin

depends on the SPI mode and can be configured as power-

down or standby.

SDIO

Input/output

SPI Serial Data Input/Output.

SCLK

Input

SPI Serial Clock.

CSB

Input

SPI Chip Select (Active Low).

No Connections

17, 18, 19, 20, 22, 45, 47,

48, 49, 50, 67, 70, 73, 82,

85, 88

DNC

Do No Connect. These pins must be left unconnected.

To ensure proper ADC operation, connect AVDD1_SR and AGND separately from the AVDD1 and EPAD connection. For more information, see the Applications

Information section.

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