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AD9691 Datasheet(PDF) 7 Page - Analog Devices

Part # AD9691
Description  Dual Analog-to-Digital Converter
PDF  73 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9691 Datasheet(HTML) 7 Page - Analog Devices

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AD9691
Data Sheet
Rev. 0 | Page 6 of 72
Parameter
Temperature
Min
Typ
Max
Unit
LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY)
Logic Compliance
Full
CMOS
Logic 1 Voltage
Full
0.8 × SPIVDD
V
Logic 0 Voltage
Full
0
0.5
V
Input Resistance
Full
30
kΩ
LOGIC OUTPUT (SDIO)
Logic Compliance
Full
CMOS
Logic 1 Voltage (IOH = 800 µA)
Full
0.8 × SPIVDD
V
Logic 0 Voltage (IOL = 50 µA)
Full
0
0.5
V
SYNC INPUTS (SYNCINB+, SYNCINB−)
Logic Compliance
Full
LVDS/LVPECL/CMOS
Differential Input Voltage
Full
400
1200
1800
mV p-p
Input Common-Mode Voltage
Full
0.6
0.85
2.0
V
Input Resistance (Differential)
Full
35
kΩ
Input Capacitance
Full
2.5
pF
LOGIC OUTPUTS (FD_A, FD_B)
Logic Compliance
Full
CMOS
Logic 1 Voltage
Full
0.8 × SPIVDD
V
Logic 0 Voltage
Full
0
0.5
V
Input Resistance
Full
30
kΩ
DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 7)
Logic Compliance
Full
CML
Differential Output Voltage
Full
360
770
mV p-p
Output Common-Mode Voltage (VCM), AC-Coupled
25°C
0
1.8
V
Short-Circuit Current (IDSHORT)
25°C
−100
+100
mA
Differential Return Loss (RLDIFF)1
25°C
8
dB
Common-Mode Return Loss (RLCM)1
25°C
6
dB
Differential Termination Impedance
Full
80
100
120
Ω
1
Differential and common-mode return loss is measured from 100 MHz to 0.75 MHz × baud rate.
SWITCHING SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate (1250 MSPS), 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, clock divider = 2, default SPI settings,
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Temperature
Min
Typ
Max
Unit
CLOCK
Clock Rate (at CLK+/CLK− Pins)
Full
0.3
4
GHz
Maximum Sample Rate1
Full
1250
MSPS
Minimum Sample Rate2
Full
300
MSPS
Clock Pulse Width
High
Full
400
ps
Low
Full
400
ps
OUTPUT PARAMETERS
Unit Interval (UI)3
Full
320
160
ps
Rise Time (tR) (20% to 80% into 100 Ω Load)
25°C
24
32
ps
Fall Time (tF) (20% to 80% into 100 Ω Load)
25°C
24
32
ps
PLL Lock Time
25°C
2
ms
Data Rate per Channel (NRZ)4
25°C
3.125
6.25
12.5
Gbps



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