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AD9691 Datasheet(PDF) 69 Page - Analog Devices |
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AD9691 Datasheet(HTML) 69 Page - Analog Devices |
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69 / 73 page  AD9691 Data Sheet Rev. 0 | Page 68 of 72 Reg Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes 0x58B JESD204B parameters SCR/L JESD204B scrambling (SCR) 0 = disabled 1 = enabled 0 0 0 0 JESD204B lanes (L) 000 = 1 lane 001 = 2 lanes 011 = 4 lanes 111 = 7 lanes Read only, see Register 0x570 0x8X 0x58C JESD204B F config Number of octets per frame, F = Register 0x58C, Bits[7:0] + 1 0x88 Read only, see Reg. 0x570 0x58D JESD204B K config 0 0 0 Number of frames per multiframe, K = Register 0x58D, Bits[4:0] + 1 Only values where (F × K) mod 4 = 0 are supported 0x1F See Reg. 0x570 0x58E JESD204B M config Number of converters per link, Bits[7:0] 0x00 = link connected to one virtual converter (M = 1) 0x01 = link connected to two virtual converters (M = 2) 0x03 = link connected to four virtual converters (M = 4) 0x07 = link connected to eight virtual converters (M = 8) Read only 0x58F JESD204B CS/N config Number of control bits (CS) per sample 00 = no control bits (CS = 0) 01 = 1 control bit (CS = 1); Control Bit 2 only 10 = 2 control bits (CS = 2); Control Bit 2 and Control Bit 1 only 11 = 3 control bits (CS = 3); all control bits (2, 1, 0) 0 ADC converter resolution (N) 0x06 = 7-bit resolution 0x07 = 8-bit resolution 0x08 = 9-bit resolution 0x09 = 10-bit resolution 0x0A = 11-bit resolution 0x0B = 14-bit resolution (default) 0x0C = 13-bit resolution 0x0D = 14-bit resolution 0x0E = 15-bit resolution 0x0F = 16-bit resolution 0x0B 0x590 JESD204B N’ config Subclass support (Subclass version) 000 = Subclass 0 (no deterministic latency) 001 = Subclass 1 ADC number of bits per sample (N’) 0x7 = 8 bits 0xF = 16 bits 0x2F 0x591 JESD204B S config 0 0 1 Samples per converter frame cycle (S) S value = Register 0x591, Bits[4:0] +1 Read only 0x592 JESD204B HD and CF configuration HD value 0 = disabled 1 = enabled 0 0 Control words per frame clock cycle per link (CF) CF value = Register 0x592, Bits[4:0] 0x80 Read only 0x5A0 JESD204B CHKSUM 0 CHKSUM value for SERDOUT0±, Bits[7:0] 0xC3 Read only 0x5A1 JESD204B CHKSUM 1 CHKSUM value for SERDOUT1±, Bits[7:0] 0xC4 Read only 0x5A2 JESD204B CHKSUM 2 CHKSUM value for SERDOUT2±, Bits[7:0] 0xC5 Read only 0x5A3 JESD204B CHKSUM 3 CHKSUM value for SERDOUT3±, Bits[7:0] 0xC6 Read only 0x5A4 JESD204B CHKSUM 4 CHKSUM value for SERDOUT4±, Bits[7:0] 0xC7 Read only 0x5A5 JESD204B CHKSUM 5 CHKSUM value for SERDOUT5±, Bits[7:0] 0xC8 Read only 0x5A6 JESD204B CHKSUM 6 CHKSUM value for SERDOUT6±, Bits[7:0] 0xC9 Read only 0x5A7 JESD204B CHKSUM 7 CHKSUM value for SERDOUT7±, Bits[7:0] 0xCA Read only 0x5B0 JESD204B lane power-down SERD- OUT7± 0 = on 1 = off SERD- OUT6± 0 = on 1 = off SERD- OUT5± 0 = on 1 = off SERDOUT4± 0 = on 1 = off SERD- OUT3± 0 = on 1 = off SERD- OUT2± 0 = on 1 = off SERD- OUT1± 0 = on 1 = off SERDOUT0± 0 = on 1 = off 0xAA |
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