AD9691 datasheet(52/73 Pages) AD

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Data Sheet

AD9691

Rev. 0 | Page 51 of 72

MULTICHIP SYNCHRONIZATION

The AD9691 has a SYSREF± input that allows flexible options

for synchronizing the internal blocks. The SYSREF± input is a

source synchronous system reference signal that enables multichip

synchronization. The input clock divider, DDCs, signal monitor

block, and JESD204B link can be synchronized using the SYSREF±

input. For the highest level of timing accuracy, SYSREF± must

meet setup and hold requirements relative to the CLK± input.

The flowchart in Figure 80 describes the internal mechanism by

which multichip synchronization can be achieved in the

AD9691. The AD9691 supports several features that aid users in

meeting the requirements for capturing a SYSREF± signal. The

SYSREF± sample event can be defined as either a synchronous

low to high transition, or synchronous high to low transition.

Additionally, the AD9691 allows the SYSREF± signal to be

sampled using either the rising edge or falling edge of the CLK±

input. The AD9691 also can ignore a programmable number (up

to 16) of SYSREF± events. The SYSREF± control options can be

selected using Register 0x120 and Register 0x121.

YES

UPDATE

SETUP/HOLD

DETECTOR STATUS

(0x128)

INCREMENT

SYSREF± IGNORE

COUNTER

YES

SYSREF±

ENABLED?

(REG 0x120)

CLOCK

DIVIDER

> 1?

(REG 0x10B)

YES

INPUT

CLOCK

DIVIDER

ALIGNMENT

REQUIRED?

YES

ALIGN CLOCK

DIVIDER

PHASE TO

SYSREF

SYNCHRONIZATION

MODE?

(REG 0x1FF)

TIMESTAMP

MODE

NORMAL

MODE

YES

SYSREF±

INSERTED

IN JESD204B

CONTROL BITS

BACK TO START

DDC NCO

ALIGNMENT

ENABLED?

(REG 0x300)

YES

SEND K28.5

CHARACTERS

NORMAL

JESD204B

INITIALIZATION

SYSREF±

CONTROL BITS?

(REG 0x559,

REG 0x55A,

REG 0x58F)

RESET

SYSREF± IGNORE

COUNTER

START

SYSREF±

ASSERTED?

YES

ALIGN SIGNAL

MONITOR

COUNTERS

YES

INCREMENT

SYSREF±

COUNTER

(REG 0x12A)

SYSREF±

TIMESTAMP

DELAY

(REG 0x123)

BACK TO START

SYSREF±

IGNORE

COUNTER

EXPIRED?

(REG 0x121)

CLOCK

DIVIDER

AUTO ADJUST

ENABLED?

(REG 0x10D)

RAMP

TEST

MODE

ENABLED?

(REG 0x550)

SYSREF± RESETS

RAMP TEST

MODE

GENERATOR

JESD204B

LMFC

ALIGNMENT

REQUIRED?

ALIGN PHASE

OF ALL

INTERNAL CLOCKS

(INCLUDING LMFC)

TO SYSREF±

SEND INVALID

8B/10B

CHARACTERS

(ALL 0s)

SYNC~

ASSERTED

SIGNAL

MONITOR

ALIGNMENT

ENABLED?

(REG 0x26F)

ALIGN DDC

NCO PHASE

ACCUMULATOR

Figure 80. Multichip Synchronization

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