AD9229 datasheet(21/41 Pages) AD

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AD9229

Rev. B | Page 20 of 40

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given full-scale

input frequency (fA) due only to aperture jitter (tA) can be

calculated with the following equation:

SNR degradation = 20 × log 10 [1/2 × π × fA × tA]

In the equation, the rms aperture jitter, tA, represents the root

sum square of all jitter sources, which include the clock input,

analog input signal, and ADC aperture jitter specification.

Applications that require undersampling are particularly

sensitive to jitter.

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the

AD9229. Power supplies for clock drivers should be separated

from the ADC output driver supplies to avoid modulating the

clock signal with digital noise. Low jitter, crystal-controlled

oscillators make the best clock sources. If the clock is generated

from another type of source (by gating, dividing, or other

methods), it should be retimed by the original clock at the

last step.

Power Dissipation and Power-Down Mode

As shown in Figure 40 and Figure 41, the power dissipated by

the AD9229 is proportional to its sample rate. The digital power

dissipation does not vary much because it is determined

primarily by the DRVDD supply and bias current of the LVDS

output drivers.

ENCODE (MSPS)

1200

900

800

600

700

1000

1100

350

250

100

200

150

300

IAVDD

TOTAL POWER

IDRVDD

Figure 40. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 50 MSPS

ENCODE (MSPS)

1400

1100

1000

800

900

1200

1300

500

300

250

200

150

100

350

400

450

IAVDD

TOTAL POWER

IDRVDD

Figure 41. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 65 MSPS

By asserting the PDWN pin high, the AD9229 is placed in

power-down mode. In this state, the ADC typically dissipates

3 mW. During power-down, the LVDS output drivers are placed

in a high impedance state. Reasserting the PDWN pin low

returns the AD9229 to normal operating mode.

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing

networks. The decoupling capacitors on REFT and REFB are

discharged when entering standby mode and then must be

recharged when returning to normal operation. As a result, the

wake-up time is related to the time spent in the power-down

mode; shorter cycles result in proportionally shorter wake-up

times. With the recommended 0.1 μF and 10 μF decoupling

capacitors on REFT and REFB, it takes approximately 1 sec to

fully discharge the reference buffer decoupling capacitors and

4 ms to restore full operation.

Digital Outputs

The AD9229’s differential outputs conform to the ANSI-644

LVDS standard. To set the LVDS bias current, place a resistor

(RSET is nominally equal to 4.0 kΩ) to ground at the

LVDSBIAS pin. The RSET resistor current is derived on-chip

and sets the output current at each output equal to a nominal

3.5 mA. A 100 Ω differential termination resistor placed at the

LVDS receiver inputs results in a nominal 350 mV swing at the

receiver. To adjust the differential signal swing, simply change

the resistor to a different value, as shown in Table 7.

Table 7. LVDSBIAS Pin Configuration

RSET

Differential Output Swing

3.7 kΩ

375 mV p-p

4.0 kΩ (default)

350 mV p-p

4.3 kΩ

325 mV p-p

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