AD9289 datasheet(16/33 Pages) AD

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AD9289

Rev. 0 | Page 15 of 32

An internal reference buffer creates the positive and negative

reference voltages, REFT and REFB, respectively, that defines

the span of the ADC core. The output common-mode of the

reference buffer is set to midsupply, and the REFT and REFB

voltages and span are defined as

REFT = 1/2 (AVDD + VREF)

REFB = 1/2 (AVDD − VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

It can be seen from the equations above that the REFT and

REFB voltages are symmetrical about the midsupply voltage

and, by definition, the input span is twice the value of the VREF

voltage.

The internal voltage reference can be pin-strapped to fixed

values of 0.5 V or 1.0 V or adjusted within the same range, as

discussed in the Internal Reference Connection section.

Maximum SNR performance is achieved by setting the AD9289

to the largest input span of 2 V p-p.

The SHA should be driven from a source that keeps the signal

peaks within the allowable range for the selected reference

voltage. The minimum and maximum common-mode input

levels are defined in Figure 26 and Figure 27.

Differential Input Configurations

Optimum performance is achieved by driving the AD9289 in a

differential input configuration. For baseband applications, the

AD8351 differential driver provides excellent performance and

a flexible interface to the ADC (see Figure 28).

AD8351

GP1

VCM

PWUP

GP2

1.2k

Ω

10k

Ω

0.1

µF

Ω

AD9289

VIN–

VIN+

AVDD

AGND

0.1

µF

0.1

µF

1V p-p

Ω

0.1

µF

0.1

µF

AVDD

Ω

Figure 28. Differential Input Configuration Using the AD8351

However, the noise performance of most amplifiers is not

adequate to achieve the true performance of the AD9289. For

applications where SNR is a key parameter, differential transfor-

mer coupling is the recommended input configuration. An

example of this is shown in Figure 29.

In any configuration, the value of the shunt capacitor, C, is

dependent on the input frequency and may need to be reduced

or removed.

AD9289

VIN+

VIN–

AVDD

AGND

2Vp-p

49.9

Ω

0.1

µF

Ω

AVDD

Figure 29. Differential Transformer-Coupled Configuration

Single-Ended Input Configuration

A single-ended input may provide adequate performance in

cost-sensitive applications. In this configuration, there is a

degradation in SFDR and distortion performance due to the

large input common-mode swing. However, if the source

impedances on each input are matched, there should be little

effect on SNR performance. Figure 30 details a typical single-

ended input configuration.

2V p-p

49.9

Ω

0.1

µF

0.1

µF

AD9289

VIN+

VIN–

AVDD

AGND

AVDD

Ω

Figure 30. Single-Ended Input Configuration

CLOCK INPUT AND CONSIDERATIONS

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals, and as a result may be

sensitive to clock duty cycle. Typically, a 5% tolerance is

required on the clock duty cycle to maintain dynamic perfor-

mance characteristics. The AD9289 has a self-contained clock

duty cycle stabilizer that retimes the nonsampling edge,

providing an internal clock signal with a nominal 50% duty

cycle. This allows a wide range of clock input duty cycles

without affecting the performance of the AD9289.

An on-board phase-locked loop (PLL) multiplies the input

clock rate for the purpose of shifting the serial data out. As a

result, any change to the sampling frequency requires a

minimum of 100 clock periods to allow the PLL to reacquire

and lock to the new rate.

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