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AM3359 Datasheet(PDF) 21 Page - Texas Instruments |
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AM3359 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 253 page  Copyright © 2011–2016, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 21 AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 www.ti.com SPRS717J – OCTOBER 2011 – REVISED APRIL 2016 Table 4-1. Pin Attributes (ZCE and ZCZ Packages) (continued) ZCE BALL NUMBER [1] ZCZ BALL NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] (25) BALL RESET REL. STATE [7] RESET REL. MODE [8] ZCE POWER / ZCZ POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULLUP /DOWN TYPE [12] I/O CELL [13] F4 E3 DDR_A12 ddr_a12 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL H1 H3 DDR_A13 ddr_a13 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL H3 H4 DDR_A14 ddr_a14 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL E3 D3 DDR_A15 ddr_a15 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL A3 C4 DDR_BA0 ddr_ba0 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL E1 E1 DDR_BA1 ddr_ba1 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL B4 B3 DDR_BA2 ddr_ba2 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL F1 F1 DDR_CASn ddr_casn 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL C2 D2 DDR_CK ddr_ck 0 O L 0 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL G3 G3 DDR_CKE ddr_cke 0 O L 0 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL C1 D1 DDR_CKn ddr_nck 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL H2 H2 DDR_CSn0 ddr_csn0 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL N4 M3 DDR_D0 ddr_d0 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/ HSTL P4 M4 DDR_D1 ddr_d1 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/ HSTL P2 N1 DDR_D2 ddr_d2 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/ HSTL P1 N2 DDR_D3 ddr_d3 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/ HSTL P3 N3 DDR_D4 ddr_d4 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/ HSTL T1 N4 DDR_D5 ddr_d5 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/ HSTL T2 P3 DDR_D6 ddr_d6 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/ HSTL R3 P4 DDR_D7 ddr_d7 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/ HSTL K2 J1 DDR_D8 ddr_d8 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/ HSTL K1 K1 DDR_D9 ddr_d9 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/ HSTL M3 K2 DDR_D10 ddr_d10 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/ HSTL |
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