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TPS23521 Datasheet(PDF) 7 Page - Texas Instruments |
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TPS23521 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 29 page ![]() 7 TPS23521 www.ti.com SLVSDX2 – SEPTEMBER 2017 Product Folder Links: TPS23521 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) –40°C ≤ TJ ≤125°C, 1.1 mA < IVCC < 10 mA, V(UVEN) = 2 V, V(OV) = V(SNS) = V(D) = 0 V, V(SS) = GATEx = Hi-Z , V(TMR) = 0 V, , VVREF = VPROG = Hi-Z; All pin voltages are relative to VEE (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R(SS,GATE) Resistance between GATE and SS in the start-up phase 10 Ω Vref/PG VVref/PG Reference output 0 < IVref/PG < 800 µA 4 4.9 5.5 V VGATE2,PG Raise GATE2 until Vref/PG goes high 7.25 V IVref/PG VVref/PG SC current Vref/PG ON, VVref/PG (shorted) 2 mA OTSD (Over temperature shut down) TSD1 Temp Rising 135 155 175 °C Hysteresis 8 °C 6.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC – Clamped Supply tID Insertion Delay VVCC: 0V → 10V, measure delay before VGATE ↑ 32 ms UVEN TUV,degl Deglitch on UVEN 4 µs OV TOV,degl Deglitch on OV 4 µs SNS TSNS,FST,R ESP Response time to large over current VSNS steps from 0mV to 60mV. Measure time for GATE and GATE2 to come down. 300 ns PGb tPGb,DEGL Deglitch of PGb. (raise GATE, measure delay between GATE and PGb) Power Good ↑ (V(GATE) 0 V → 10 V) Look for PGb ↓ 1 ms Power Good ↓ (V(GATE) 10 V → 0 V) Look for PGb ↑ 32 ms |
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