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TPS23521

SLVSDX2 – SEPTEMBER 2017

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Device Functional Modes (continued)

•

TimeOut: This signal comes from the time out block and will be asserted Hi if the IC has timed out due to an

over-current condition. This signal is also Hi while the timer is going through the restart cycles. Once the

cycles are completed this signal will go Low.

•

ins_over: This signal states that the insertion delay has been completed and the Hot Swap is ready to start-

up.

•

FT: this is the fast trip signal coming from the fast trip comparator. It goes Hi if an extreme over current event

is detected.

•

PG: Internal Power good signal. This is high when the Hot Swap is fully on and the load can draw full power.

For PG to be Hi, the GATE has to be Hi, GATE2 needs to be Hi, and the drain pin needs to be below 0.75V.

•

PG_degl: This is a deglitched version of the PG and is the signal used to move between states and controls

the external PGb pin.

7.4.1 OFF State

In this state the Hot Swap FET is turned off and the controller is waiting to start-up. The controller can be in this

state due to any of these scenarios:

•

Input voltage is not in the valid range.

•

The Hot Swap is in the cool down state and the time is going through the retry cycle after a fault condition

such as output hot short or over current.

•

VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.

7.4.2 Insertion Delay State

In this state the Hot Swap FET is turned off and the controller is waiting for the insertion delay to finish. This

allows the input supply to settle after a Hot Plug. If any of the following occur, the controller will be kicked back to

the OFF state:

•

Input voltage is not in the valid range.

•

VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.

Once the insertion delay is finished, the controller will move to the Start-up state.

7.4.3 Start-up State

In this state the controller is turning on and charging the output cap. The operation is set as follows:

•

The SS pin is internally connected to the GATE pin to allow for output dv/dt control.

•

The SS pin is internally connected to the GATE pin to allow for output dv/dt control.

•

MOSFET stress in case of a fault condition.

If any of the following occur, the controller will be kicked back to the OFF state:

•

Input voltage is not in the valid range.

•

The timer times out due to over-current.

•

VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.

•

Fast trip is triggered.

Once the PG_degl signal goes Hi, the controller will move to the Normal Operation state.

7.4.4 Normal Operation State

In this state the Hot Swap is fully on and the operation is set as follows:

•

The SS pin is disconnected from the GATE pin to improve transient response.

•

The full gate sourcing current is used to improve transient response.

•

The current limit and fast trip threshold are a function of the D pin to optimize the transient response while

protecting the MOSFET.

If any of the following occur, the controller will be kicked back to the OFF state:

•

• PG_degl goes low.

•

The timer times out due to over-current.

•

VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.