TMSC6701 datasheet(38/64 Pages) TI

38 / 64 page

TMS320C6701

FLOATINGPOINT DIGITAL SIGNAL PROCESSOR

SPRS067E – MAY 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SYNCHRONOUS DRAM TIMING

timing requirements for synchronous DRAM cycles (see Figure 18)

NO.

’C6701-120

’C6701-150

’C6701-167

UNIT

MIN

MAX

tsu(EDV-SDCLKH)

Setup time, read EDx valid before SDCLK high

1.8

th(SDCLKH-EDV)

Hold time, read EDx valid after SDCLK high

switching characteristics for synchronous DRAM cycles† (see Figure 18–Figure 23)

NO.

PARAMETER

’C6701-120

’C6701-150

’C6701-167

UNIT

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

tosu(CEV-SDCLKH)

Output setup time, CEx valid before SDCLK high

1.5P – 4

toh(SDCLKH-CEV)

Output hold time, CEx valid after SDCLK high

0.5P – 1.9

0.5P – 1.5

tosu(BEV-SDCLKH)

Output setup time, BEx valid before SDCLK high

1.5P – 4

toh(SDCLKH-BEIV)

Output hold time, BEx invalid after SDCLK high

0.5P – 1.9

0.5P – 1.5

tosu(EAV-SDCLKH)

Output setup time, EAx valid before SDCLK high

1.5P – 4

toh(SDCLKH-EAIV)

Output hold time, EAx invalid after SDCLK high

0.5P – 1.9

0.5P – 1.5

tosu(SDCAS-SDCLKH)

Output setup time, SDCAS valid before SDCLK

high

1.5P – 4

toh(SDCLKH-SDCAS)

Output hold time, SDCAS valid after SDCLK high

0.5P – 1.9

0.5P – 1.5

tosu(EDV-SDCLKH)

Output setup time, EDx valid before SDCLK high

1.5P – 4

toh(SDCLKH-EDIV)

Output hold time, EDx invalid after SDCLK high

0.5P – 1.9

0.5P – 1.5

tosu(SDWE-SDCLKH)

Output setup time, SDWE valid before SDCLK high

1.5P – 4

toh(SDCLKH-SDWE)

Output hold time, SDWE valid after SDCLK high

0.5P – 1.9

0.5P – 1.5

tosu(SDA10V-SDCLKH)

Output setup time, SDA10 valid before SDCLK high

1.5P – 4

toh(SDCLKH-SDA10IV)

Output hold time, SDA10 invalid after SDCLK high

0.5P – 1.9

0.5P – 1.5

tosu(SDRAS-SDCLKH)

Output setup time, SDRAS valid before SDCLK

high

1.5P – 4

toh(SDCLKH-SDRAS)

Output hold time, SDRAS valid after SDCLK high

0.5P – 1.9

0.5P – 1.5

† When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

For CLKMODE x1:

1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.

0.5P = PL, where PL = pulse duration of CLKIN low.

TMSC6701 Datasheet(PDF) 38 Page - Texas Instruments

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