TMSC6701 datasheet(46/64 Pages) TI

46 / 64 page

TMS320C6701

FLOATINGPOINT DIGITAL SIGNAL PROCESSOR

SPRS067E – MAY 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

HOST-PORT INTERFACE TIMING

timing requirements for host-port interface cycles†‡ (see Figure 27, Figure 28, Figure 29, and

Figure 30)

NO.

’C6701-120

’C6701-150

’C6701-167

UNIT

MIN

MAX

tsu(SEL-HSTBL)

Setup time, select signals§ valid before HSTROBE low

th(HSTBL-SEL)

Hold time, select signals§ valid after HSTROBE low

tw(HSTBL)

Pulse duration, HSTROBE low

tw(HSTBH)

Pulse duration, HSTROBE high between consecutive accesses

tsu(SEL-HASL)

Setup time, select signals§ valid before HAS low

th(HASL-SEL)

Hold time, select signals§ valid after HAS low

tsu(HDV-HSTBH)

Setup time, host data valid before HSTROBE high

th(HSTBH-HDV)

Hold time, host data valid after HSTROBE high

th(HRDYL-HSTBL)

Hold time, HSTROBE low after HRDY low. HSTROBE should not be inacti-

vated until HRDY is active (low); otherwise, HPI writes will not complete

properly.

tsu(HASL-HSTBL)

Setup time, HAS low before HSTROBE low

th(HSTBL-HASL)

Hold time, HAS low after HSTROBE low

† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

§ Select signals include: HCNTRL[1:0], HR/W, and HHWIL.

switching characteristics during host-port interface cycles†‡ (see Figure 27, Figure 28, Figure 29,

and Figure 30)

NO.

PARAMETER

’C6701-120

’C6701-150

’C6701-167

UNIT

MIN

MAX

td(HCS-HRDY)

Delay time, HCS to HRDY¶

td(HSTBL-HRDYH)

Delay time, HSTROBE low to HRDY high#

td(HSTBL-HDLZ)

Delay time, HSTROBE low to HD low impedance for an HPI read

td(HDV-HRDYL)

Delay time, HD valid to HRDY low

P – 3

P + 3

toh(HSTBH-HDV)

Output hold time, HD valid after HSTROBE high

td(HSTBH-HDHZ)

Delay time, HSTROBE high to HD high impedance

td(HSTBL-HDV)

Delay time, HSTROBE low to HD valid

td(HSTBH-HRDYH)

Delay time, HSTROBE high to HRDY high||

td(HASL-HRDYH)

Delay time, HAS low to HRDY high

† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

¶ HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy

completing a previous HPID write or READ with autoincrement.

# This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the

request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID.

|| This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write

or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.

TMSC6701 Datasheet(PDF) 46 Page - Texas Instruments

TMSC6701 Datasheet(HTML) 46 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL