TMSC6701 datasheet(49/64 Pages) TI

49 / 64 page

TMS320C6701

FLOATINGPOINT DIGITAL SIGNAL PROCESSOR

SPRS067E – MAY 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

MULTICHANNEL BUFFERED SERIAL PORT TIMING

timing requirements for McBSP†‡ (see Figure 31)

NO.

’C6701-120

’C6701-150

’C6701-167

UNIT

MIN

MAX

tc(CKRX)

Cycle time, CLKR/X

CLKR/X ext

2P§

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X ext

P – 1¶

Setup time external FSR high before CLKR low

CLKR int

tsu(FRH-CKRL)

Setup time, external FSR high before CLKR low

CLKR ext

Hold time external FSR high after CLKR low

CLKR int

th(CKRL-FRH)

Hold time, external FSR high after CLKR low

CLKR ext

Setup time DR valid before CLKR low

CLKR int

tsu(DRV-CKRL)

Setup time, DR valid before CLKR low

CLKR ext

Hold time DR valid after CLKR low

CLKR int

th(CKRL-DRV)

Hold time, DR valid after CLKR low

CLKR ext

Setup time external FSX high before CLKX low

CLKX int

tsu(FXH-CKXL)

Setup time, external FSX high before CLKX low

CLKX ext

Hold time external FSX high after CLKX low

CLKX int

th(CKXL-FXH)

Hold time, external FSX high after CLKX low

CLKX ext

† P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

‡ CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

§ The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz),

whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting

the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum

CLKR/X clock cycle. The maximum McBSP bit rate applies when the serial port is a master of clock and frame syncs and the other device the

McBSP communicates to is a slave.

¶ The minimum CLKR/X pulse duration is either (P–1) or 9 ns, whichever is larger. For example, when running parts at 167 MHz (P = 6 ns), use

9 ns as the minimum CLKR/X pulse duration. When running parts at 80 MHz (P = 12.5 ns), use (P–1) = 11.5 ns as the minimum CLKR/X pulse

duration.

TMSC6701 Datasheet(PDF) 49 Page - Texas Instruments

TMSC6701 Datasheet(HTML) 49 Page - Texas Instruments

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