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TMSC6701 Datasheet(PDF) 32 Page - Texas Instruments |
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TMSC6701 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 64 page ![]() TMS320C6701 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS067E – MAY 1998 – REVISED MAY 2000 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles† (see Figure 12 and Figure 13) NO. ’C6701-120 ’C6701-150 ’C6701-167 UNIT MIN MAX 6 tsu(EDV-CKO1H) Setup time, read EDx valid before CLKOUT1 high 4.5 ns 7 th(CKO1H-EDV) Hold time, read EDx valid after CLKOUT1 high 1.5 ns 10 tsu(ARDY-CKO1H) Setup time, ARDY valid before CLKOUT1 high 3.5 ns 11 th(CKO1H-ARDY) Hold time, ARDY valid after CLKOUT1 high 1.5 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input. switching characteristics for asynchronous memory cycles‡ (see Figure 12 and Figure 13) NO. PARAMETER ’C6701-120 ’C6701-150 ’C6701-167 UNIT MIN MAX 1 td(CKO1H-CEV) Delay time, CLKOUT1 high to CEx valid –1.0 4.5 ns 2 td(CKO1H-BEV) Delay time, CLKOUT1 high to BEx valid 4.5 ns 3 td(CKO1H-BEIV) Delay time, CLKOUT1 high to BEx invalid –1.0 ns 4 td(CKO1H-EAV) Delay time, CLKOUT1 high to EAx valid 4.5 ns 5 td(CKO1H-EAIV) Delay time, CLKOUT1 high to EAx invalid –1.0 ns 8 td(CKO1H-AOEV) Delay time, CLKOUT1 high to AOE valid –1.0 4.5 ns 9 td(CKO1H-AREV) Delay time, CLKOUT1 high to ARE valid –0.5 4.5 ns 12 td(CKO1H-EDV) Delay time, CLKOUT1 high to EDx valid 4.5 ns 13 td(CKO1H-EDIV) Delay time, CLKOUT1 high to EDx invalid –1.0 ns 14 td(CKO1H-AWEV) Delay time, CLKOUT1 high to AWE valid –1.0 4.5 ns ‡ The minimum delay is also the minimum output hold after CLKOUT1 high. |
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