Pin-Programmable, Ultralow Noise, 24-Bit,

Sigma-Delta ADC for Bridge Sensors

AD7191

Rev. A

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FEATURES

Pin-programmable output rate

Output data rate: 10 Hz, 50 Hz, 60 Hz, 120 Hz

Pin-programmable PGA

Gain: 1, 8, 64, 128

Pin-programmable power-down and reset

RMS noise: 15 nV @ 10 Hz (gain = 128)

Up to 21.5 noise free bits (gain = 1)

Internal or external clock

Bridge power-down switch

Offset drift: 5 nV/°C

Gain drift: 1 ppm/°C

Specified drift over time

Simultaneous 50 Hz/60 Hz rejection

Internal temperature sensor

Power supply: 3 V to 5.25 V

Current: 4.35 mA

Temperature range: –40°C to +105°C

Package: 24-lead TSSOP

INTERFACE

2-wire serial

SPI, QSPI™, and MICROWIRE™ compatible

Schmitt trigger on SCLK

APPLICATIONS

Weigh scales

Strain gauge transducers

Pressure measurement

Medical and scientific instrumentation

GENERAL DESCRIPTION

The AD7191 is a low noise, complete analog front end for high

precision measurement applications. It contains a low noise,

24-bit sigma-delta (Σ-Δ) ADC. The on-chip low noise gain

stage means that signals of small amplitude can be interfaced

directly to the ADC. It contains two differential analog inputs.

The part also includes a temperature sensor that can be used for

temperature compensation.

For ease-of-use, all the features of the AD7191 are controlled by

dedicated pins. The on-chip PGA has a gain of 1, 8, 64, or 128,

supporting a full-scale differential input of ±5 V, ±625 mV,

±78 mV, or ±39 mV. The output data rate can be programmed

to 10 Hz, 50 Hz, 60 Hz, or 120 Hz. Simultaneous 50 Hz and 60 Hz

rejection is obtained when the output data rate is set to 10 Hz

or 50 Hz; 60 Hz only rejection is obtained when the output data

rate is set to 60 Hz. The AD7191 can be operated with the

internal clock, or an external clock can be used.

The part operates with a power supply of 3 V to 5.25 V. It

consumes a current of 4.35 mA. It is available in a 24-lead

TSSOP package.

FUNCTIONAL BLOCK DIAGRAM

MUX

AD7191

AIN1

DOUT/RDY

SCLK

PDOWN

CHAN

CLKSEL

PGA2

PGA1

AGND

DGND

REFIN(+) REFIN(–)

AIN2

AIN3

AIN4

BPDSW

MCLK1

MCLK2

ODR2 ODR1 TEMP

TEMPERATURE

SENSOR

CLOCK

CIRCUITRY

PGA

SERIAL

INTERFACE

AND CONTROL

LOGIC

Σ-Δ

ADC

Figure 1.